Semiconductor device including pipe latch circuit
AssigneeSK hynix Inc.
InventorsHyun Seung Kim, Ju Hyuck Kim
Life of this patent
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Abstract
A semiconductor device includes an input control signal generation circuit configured to generate an input control signal when performing an internal operation and configured to adjust a time point at which the input control signal is generated, based on whether a frequency of a clock corresponds to a preset frequency range. The semiconductor device includes an output control signal generation circuit configured to generate an output control signal after a latency elapses when performing the internal operation. The semiconductor device includes a pipe latch circuit configured to latch input data based on the input control signal and configured to output the latched input data as output data based on the output control signal.
Claims20
A semiconductor device comprising:
- an input control signal generation circuit configured to generate an input control signal when performing an internal operation and configured to adjust a time point at which the input control signal is generated, based on whether a frequency of a clock corresponds to a preset frequency range;
- an output control signal generation circuit configured to generate an output control signal after a latency elapses when performing the internal operation;
- and
- a pipe latch circuit configured to latch input data based on the input control signal and configured to output the latched input data as output data based on the output control signal.
A semiconductor device comprising:
- an input data generation circuit configured to generate input data when performing an internal operation and configured to adjust a time point at which the input data is generated, based on whether a frequency of a clock corresponds to a preset frequency range;
- a first latch circuit configured to generate first latch data by latching the input data based on a first bit of an input control signal and configured to output the first latch data as output data based on a first bit of an output control signal;
- and
- a second latch circuit configured to generate second latch data by latching the input data based on a second bit of the input control signal and configured to output the second latch data as the output data based on a second bit of the output control signal.
Dependencies are inferred from the claim text.