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US 11,776,591 B2Granted
Concurrent access techniques utilizing wordlines with the same row address in single port memory
AssigneeArm Limited
InventorsLalit Gupta, Bo Zheng, El Mehdi Boujamaa, Fakhruddin Ali Bohra
Life of this patent
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Abstract
Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.
Claims19
A method, comprising:
- providing single port memory with a plurality of different banks having a first bank of bitcells and a second bank of bitcells that is different than the first bank of bitcells;
- coupling a plurality of wordlines to the single port memory including coupling a first wordline to each bitcell in the first bank and coupling a second wordline to each bitcell in the second bank;
- coupling a plurality of shared bitlines to the single port memory including coupling a plurality of first shared bitlines to each bitcell in the first bank and coupling a plurality of second shared bitlines to each bitcell in the second bank;
- coupling a plurality of shared read bitlines to the single port memory including coupling a plurality of first shared read bitlines to the first shared bitlines for each bitcell in the first bank and coupling a plurality of second shared read bitlines to the second shared bitlines for each bitcell in the second bank;
- and
- performing a plurality of memory access operations concurrently in the single port memory including performing a read operation in the first bank using the first wordline and the plurality of first shared read bitlines while performing a write operation in the second bank using the second wordline and the plurality of second shared bitlines, or performing a write operation in the first bank using the first wordline and the plurality of first shared bitlines while performing a read operation in the second bank using the second wordline and the plurality of second read shared bitlines.
3 more elements
A device, comprising:
- single port memory architecture having a plurality of bitcell arrays including a first bitcell array and a second bitcell array that is different than the first bitcell array;
- a first wordline coupled to each bitcell in the first bitcell array and a second wordline coupled to each bitcell in the second bitcell array;
- a plurality of first shared bitlines coupled to each bitcell in the first bank and a plurality of second shared bitlines coupled to each bitcell in the second bank;
- and
- a plurality of first shared read bitlines coupled to the first shared bitlines in the first bank and a plurality of second shared read bitlines coupled to the second shared bitlines in the second bank;
- and
- logic circuitry that performs a plurality of memory access operations concurrently in the single port memory architecture including performing a read operation in the first bitcell array using the first wordline and the plurality of first shared read bitlines while performing a write operation in the second bitcell array using the second wordline and the plurality of second shared bitlines, or performing a write operation in the first bitcell array using the first wordline and the plurality of first shared bitlines while performing a read operation in the second bitcell array using the second wordline and the plurality of second shared read bitlines.
4 more elements
A system, comprising:
- a processor;
- and
- memory having stored thereon instructions that, when executed by the processor, cause the processor to:
- access single port memory having a plurality of different banks with a first bank of bitcells and a second bank of bitcells that is different than the first bank of bitcells;
- access a plurality of wordlines of the single port memory by accessing a first wordline coupled to each bitcell in the first bank and accessing a second wordline coupled to each bitcell in the second bank;
- access a plurality of shared bitlines of the single port memory by accessing a plurality of first shared bitlines coupled to each bitcell in the first bank and by accessing a plurality of second shared bitlines coupled to each bitcell in the second bank;
- access a plurality of shared read bitlines of the single port memory by accessing a plurality of first shared read bitlines coupled to the first shared bitlines in the first bank and by accessing a plurality of second shared read bitlines coupled to the second shared bitlines in the second bank;
- and
- perform a plurality of memory access operations concurrently in the single port memory by performing a read operation in the first bank using the first wordline and the plurality of first shared read bitlines while performing a write operation in the second bank using the second wordline and the plurality of second shared bitlines, or performing a write operation in the first bank using the first wordline and the plurality of first shared bitlines while performing a read operation in the second bank using the second wordline and the plurality of second shared read bitlines.
6 more elements
Dependencies are inferred from the claim text.