Vertical compression scheme for compressed soft bit data in non-volatile memories with data latch groups

A method, comprising:

• performing a read operation by each of a plurality of sense amplifiers on a plurality of memory cells;
• storing results of the read operation by each of the sense amplifiers in a corresponding set of internal data latches, each set of internal data latches comprising a first subset of internal data latches connected along a first local data bus and a second subset of internal data latches connected along a second local data bus;
• performing, within the corresponding set of internal data latches, a data compression operation of the results of the read operations by each of the sense amplifiers in which, for each set of internal data latches, the results of the read operation stored in the first subset of the corresponding internal data latches are compressed within the first subset of the corresponding set of internal data latches and the results of the read operation stored in the second subset of the corresponding internal data latches are compressed within the second subset of the corresponding set of internal data latches;
• combining, for each of the corresponding sets of internal data latches, the compressed results of the read operation from the first subset of the corresponding internal data latches with the compressed results of the read operation from the second subset of the corresponding internal data latches;
• and
• transferring the combined compressed results of the read operations from the sets of internal data latches to an input-output interface.

A non-volatile memory device, comprising:

• a plurality of bit lines each connected to a corresponding plurality of non-volatile memory cells;
• a plurality of sense amplifier circuits each configured to read data from memory connected to a corresponding one or more bit lines;
• a plurality of sets of data latches, each set of data latches configured to store data associated with a corresponding one of the sense amplifiers and each set of data latches comprising a first subset of data latches connected along a first local data bus and a second subset of data latches connected along a second local data bus;
• logic and multiplexing circuitry connected, for each of the corresponding sets of data latches, to the first subset of data latches and the second subset of data latches;
• an input-output interface configured to provide data to an external data bus;
• and
• one or more control circuits connected to the sense amplifier circuits, the sets of data latches, the logic and multiplexing circuitry, and the input-output interface, the one or more control circuits configured to:
• perform a read operation by each of the plurality of sense amplifiers on a plurality of the corresponding memory cells;
• store results of the read operation by each of the sense amplifiers in the corresponding set of data latches;
• compress the results of the read operation stored in the first subset of the corresponding data latches within the first subset of the corresponding set of data latches;
• compress the results of the read operation stored in the second subset of the corresponding data latches within the second subset of the corresponding set of data latches;
• combine, by the logic and multiplexing circuitry, the compressed results of the read operation from the first subset of the corresponding data latches with the compressed results of the read operation from the second subset of the corresponding data latches for each of the corresponding sets of data latches;
• and
• transfer the combined compressed results of the read operation over the input-output interface to the external data bus.