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US 11,776,584 B2Granted
Bank and channel structure of stacked semiconductor device
AssigneeMicron Technology, Inc.
InventorKayoko Shibata
Life of this patent
Estimating the term…
Abstract
Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.
Claims21
An apparatus comprising:
- a first memory core chip including a first memory bank assigned to a first channel;
- a second memory core chip including a second memory bank assigned to the first channel;
- a third memory core chip including a third memory bank assigned to a second channel;
- and
- a fourth memory core chip including a fourth memory bank assigned to the second channel,
- wherein the first, second, third, and fourth memory core chips are stacked with one another such that the second memory core chip is between the first and third memory core chips and the third memory core chip is between the second and fourth memory core chips,
- wherein the first memory core chip and the third memory core chip are configured to be activated for data transfer responsive to a first plurality of commands that are indicative of a first bank address associated with a first memory cell bank group, and
- wherein the second memory core chip and the fourth memory core chip are configured to be activated for data transfer responsive to a second plurality of commands that are indicative of a second bank address associated with a second memory cell bank group that is different from the first memory cell bank group.
5 more elements
An apparatus comprising:
- an interface chip configured to receive clock signals, command signals, and data signals via a plurality of channels including a first channel and a second channel;
- and
- a plurality of memory core chips stacked on the interface chip wherein the plurality of memory core chips and the interface chip are coupled to each other, the plurality of memory core chips including:
- a first memory core chip including a first memory cell bank group addressed by a first bank address and configured to be accessed in the first channel;
- a second memory core chip disposed between the first memory core chip and the interface chip, the second memory core chip including a second memory cell bank group addressed by a second bank address and configured to be accessed in the first channel;
- and
- a third memory core chip disposed between the second memory core chip and the interface chip, the third memory core chip including a third memory bank group addressed by the first bank address and configured to be accessed in the second channel;
- wherein the first memory core chip and the third memory core chip are configured to be activated for data transfer responsive to a first plurality of commands that are indicative of the first bank address, and
- wherein the second memory core chip is configured to be activated for data transfer responsive to a second plurality of commands that are indicative of the second bank address.
6 more elements
An apparatus comprising:
- a memory controller configured to provide clock signals, command signals, and data signals via a plurality of channels including a first channel and a second channel;
- an interface chip configured to be coupled to the memory controller and configured to receive the clock signals, the command signals and the data signals via the plurality of channels including the first channel and the second channel from the memory controller;
- and
- a plurality of memory core chips stacked on the interface chip wherein the plurality of memory core chips and the interface chip are coupled to one another by a plurality of through electrodes, the plurality of memory core chips including:
- a first memory core chip including a first memory cell bank group configured to be accessed in a first channel through the plurality of through electrodes;
- a second memory core chip adjacent to the first memory core chip and disposed between the first memory core chip and the interface chip, the second memory core chip including a second memory cell bank group configured to be accessed in the first channel through the plurality of through electrodes;
- and
- a third memory core chip disposed between the second memory core chip and the interface chip, the third memory core chip including a third memory cell bank group configured to be accessed in a second channel through the plurality of through electrodes;
- wherein the first memory core chip and the third memory core chip are configured to be activated for data transfer responsive to a first plurality of commands that are indicative of a first bank address associated with a first memory cell bank group, and
- wherein the second memory core chip is configured to be activated for data transfer responsive to a second plurality of commands that are indicative of a second bank address associated with a second memory cell bank group that is different from the first memory cell bank group.
7 more elements
Dependencies are inferred from the claim text.