Semiconductor memory devices

A semiconductor memory device comprising:

• a substrate in which a plurality of active regions are defined:
• a plurality of word lines intersecting with the plurality of active regions and extending in parallel in a first lateral direction:
• a plurality of bit line structures comprising bit lines on the substrate, the bit lines extending in parallel in a second lateral direction perpendicular to the first lateral direction;
• a plurality of buried contacts and a plurality of landing pads, wherein the plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures;
• and
• a plurality of storage nodes on the plurality of landing pads,
• wherein the plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of three adjacent landing pads, from among the plurality of landing pads, are connected by a scalene triangle, and
• wherein the plurality of storage nodes have a hexagonal array structure, and central points of respective top surfaces of three adjacent storage nodes, from among the plurality of storage nodes, are connected by an equilateral triangle.

A semiconductor memory device comprising:

• a substrate in which a plurality of active regions are defined by a device isolation film;
• a plurality of word lines intersecting with the plurality of active regions and extending in parallel in a first lateral direction:
• a plurality of bit line structures located on the substrate, the plurality of bit line structures having bit lines extending in parallel in a second lateral direction perpendicular to the first lateral direction;
• a plurality of buried contacts filling lower portions of spaces between the plurality of bit line structures on the substrate, the plurality of buried contacts being connected to the plurality of active regions;
• a plurality of landing pads connected to the plurality of buried contacts, the plurality of landing pads filling upper portions of the spaces between the plurality of bit line structures and extending onto the plurality of bit line structures, wherein a top surface of each of the plurality of landing pads has a disc shape;
• and
• a plurality of storage nodes located on the plurality of bit line structures and connected to the plurality of landing pads,
• wherein first, second, and third sides of a triangle connecting central points of respective top surfaces of three adjacent landing pads, from among the plurality of landing pads, have a length of 3F, a length of less than 3F, and a length of more than 3F, respectively, wherein F represents a feature size, and
• each of first, second, and third sides of a triangle connecting central points of respective top surfaces of three adjacent storages nodes, from among the plurality of storage nodes, has a length of 3F.