Techniques to manage execution of divergent shaders
AssigneeIntel Corporation
InventorsJohn G. Gierach, Karthik Vaidyanathan, Thomas F. Raoux
Life of this patent
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Abstract
Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.
Claims19
An apparatus comprising:
- a memory device;
- processors including a plurality of single instruction multiple data (SIMD) processors;
- circuitry to dispatch at least one thread for execution by at least a portion of the processors, wherein:
- the at least one thread comprises a first shader,
- execution of the first shader is to cause access to a buffer that identifies pixel data and a counter value associated with a first subroutine,
- in response to a request to perform the first subroutine, the circuitry is to dispatch for execution the first subroutine with a number of other instances of the first subroutine based on the counter value, and
- the first subroutine and the number of other instances of the first subroutine are to process identified pixel data.
At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
- analyze a first shader to determine any branch with two divergent subroutines, the two divergent subroutines comprising a first subroutine and a second subroutine;
- associate the first subroutine with identifiers of a first group of one or more pixels and a first count value and associate the second subroutine with identifiers of a second group of one or more pixels and a second count value;
- execute the first subroutine in parallel with a number of instances of the first subroutine based on the first count value;
- and
- execute the second subroutine in parallel with a number of instances of the second subroutine based on the second count value.
A system comprising:
- at least one memory;
- at least one processor;
- and
- at least one graphics processing unit communicatively coupled to the at least one memory and to the at least one processor, wherein:
- the at least one processor is to:
- request execution of a shader to process data stored in the at least one memory using a portion of the at least one graphics processing unit, the shader comprising a first subroutine;
- access a buffer that identifies pixel data and a counter value associated with the first subroutine;
- and
- dispatch execution of the first subroutine in parallel with a number of other instances of the first subroutine based on the counter value using a portion of the at least one graphics processing unit.
Dependencies are inferred from the claim text.