Scheduling heterogeneous execution on heterogeneous hardware

A system comprising;

• a processor;
• a memory device containing instructions, which when executed by the processor cause the processor to:
• determine input parameters and an output format of algorithms for a particular functionality provided by the system;
• determine an order of the algorithms for performing the particular functionality based at least in part on temporal dependencies of the algorithms, and the input parameters and the output format of the algorithms;
• generate a graph based at least in part on the order of the algorithms, the graph including a set of nodes corresponding to the algorithms, each node indicating a particular processor of the system for executing an algorithm;
• and
• execute the particular functionality based on performing a traversal of the graph, the traversal including a selection of a particular node for execution over another node based on execution of the particular node resulting in a greater number of processors of the system being concurrently in use than execution of the other node, wherein the processors include at least two of:
• a CPU, a GPU, or a neural processor.

A non-transitory computer-readable medium comprising instructions, which when executed by a computing device, cause the computing device to perform operations comprising:

• determining input parameters and an output format of algorithms for a particular functionality provided by an electronic device, the electronic device comprising a plurality of processors, the plurality of processors including at least two of:
• a CPU, a GPU, or a neural processor;
• determining an order of the algorithms for performing the particular functionality based at least in part on temporal dependencies of the algorithms, and the input parameters and the output format of the algorithms;
• generating a graph based at least in part on the order of the algorithms, the graph comprising a set of nodes corresponding to the algorithms, each node indicating a particular processor of the plurality of processors for executing an algorithm of the node;
• and
• executing the particular functionality based on performing a traversal of the graph, the traversal comprising a topological traversal of the set of nodes and the traversal including a selection of a particular node for execution over another node based on execution of the particular node minimizing a collective downtime of the plurality of processors relative to execution of the other node.