System and method for accelerating RNN network, and storage medium

A recurrent neural network accelerating system, comprising a first cache, a second cache, a vector multiplication circuit, an addition circuit, an activation circuit, a state updating circuit, a biased data cache, a vector cache and a Cell state cache, wherein,

• the first cache is configured to circularly switch between a first state and a second state, output Wx1 to WxN in N paths in the first state in parallel with degrees of parallelism of k, and output Wh1 to WhN in N paths in the second state in parallel with degrees of parallelism of k, wherein N is a positive integer greater than or equal to 2;
• the second cache is configured to circularly switch between the first state and the second state, output xt in the first state, and output ht-1 in the second state;
• the vector multiplication circuit is configured to use N groups of multiplication arrays to respectively calculate Wx1xt to WxNxt when receiving Wx1 to WxN output by the first cache, and use the N groups of multiplication arrays to respectively calculate Wh1ht-1 to WhNht-1 when receiving Wh1 to WhN output by the first cache, wherein the vector multiplication circuit comprises the N groups of multiplication arrays, each group of the multiplication arrays comprise k multiplication units;
• the addition circuit is configured to receive b1 to bN sent by a biased data cache, and use a vector cache to realize the calculation of Wx1xt+Wh1ht-1+b1 to WxNxt+WhNht-1+bN;
• the activation circuit is configured to perform activation operation according to an output of the addition circuit;
• the state updating circuit is configured to obtain ct-1 from a Cell state cache, calculate ct and ht according to the output of the activation circuit, use ct to update ct-1 in the Cell state cache after calculating out ct, and send ht to the second cache;
• wherein Wx1 to WxN sequentially represent weight data matrixes of a first gate to a N-th gate, Wh1 to WhN sequentially represent hidden state weight data matrixes of the first gate to the N-th gate, b1 to bN sequentially represent biased data of the first gate to the N-th gate, xt represents input data at time t, ht-1 represents hidden state data at time t−1, ht represents hidden state data at time t, ct represents a Cell state at time t, and ct-1 represents a Cell state at time t−1.