US 11,775,802 B2Granted

Neural processor

AssigneeSamsung Electronics Co., Ltd.

InventorsIlia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li

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Abstract

A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Claims20

Dependent claims

A processor, comprising:

a first tile,
a second tile,
a memory,
an input bus, and
an output bus,
the input bus being connected to:
the memory,
the first tile, and
the second tile,
the first tile comprising:
a first weight register,
a second weight register,
an activations buffer,
a first multiplier, and
a second multiplier,
the first tile being configured to perform a first convolution of an array of activations with a kernel of weights;
the memory comprising:
a first memory bank set, and
a second memory bank set;
the input bus comprising:
a first segmented bus for data propagating in a first direction, and
a second segmented bus for data propagating in a second direction, opposite the first direction;
the first segmented bus comprising:
a first switch block, and
a second switch block;
the first switch block being connected to:
the first tile, and
the first memory bank set;
the second switch block being connected to:
the second tile, and
the second memory bank set;
the second segmented bus comprising:
a third switch block, and
a fourth switch block;
the third switch block being connected to:
the first tile, and
the first memory bank set;
the fourth switch block being connected to:
the second tile, and
the second memory bank set;
an input of the first switch block being connected to an output of the second switch block;
and
an output of the third switch block being connected to an input of the fourth switch block.

40 more elements

A method for calculating with a processing circuit, the processing circuit comprising:

a first tile,
a second tile,
a memory,
an input bus, and
an output bus,
the input bus being connected to:
the memory,
the first tile, and
the second tile,
the first tile comprising:
a first weight register,
a second weight register,
an activations buffer,
a first multiplier, and
a second multiplier,
the first tile being configured to perform a first convolution of an array of activations with a kernel of weights;
the memory comprising:
a first memory bank set, and
a second memory bank set;
the input bus comprising:
a first segmented bus for data propagating in a first direction, and
a second segmented bus for data propagating in a second direction, opposite the first direction;
the first segmented bus comprising:
a first switch block, and
a second switch block;
the first switch block being connected to:
the first tile, and
the first memory bank set;
the second switch block being connected to:
the second tile, and
the second memory bank set;
the second segmented bus comprising:
a third switch block, and
a fourth switch block;
the third switch block being connected to:
the first tile, and
the first memory bank set;
the fourth switch block being connected to:
the second tile, and
the second memory bank set;
an input of the first switch block being connected to an output of the second switch block;
and
an output of the third switch block being connected to an input of the fourth switch block,
the method comprising:
in a first bus state,
connecting, by the first switch block, the first memory bank set to the first tile, and
connecting, by the second switch block, the second memory bank set to the second tile.

44 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/552,945Filed 27 Aug 2019 · continuation
Priority: 22 Jun 2018
Published: US 2020/0026980 A123 Jan 2020
Granted: 3 Oct 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06N 3/04
Neural networks: architecture, e.g. interconnection topology
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06F 17/153
Correlation function computation including computation of convolution operations: multidimensional correlation or convolution
G06F 17/16
Complex mathematical operations: matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

Family

Application62/689,008Us provisional application · filed 22 Jun 2018
Application62/798,297Us provisional application · filed 29 Jan 2019
Application62/841,590Us provisional application · filed 1 May 2019
Application62/841,606Us provisional application · filed 1 May 2019
Application16/446,610Parent of this continuation · filed 19 Jun 2019
US 2020/0026980 A1Pre-grant publication · published 23 Jan 2020
US 11,783,161 B2Related patent
US 11,954,574 B2Related patent
US 12,099,912 B2Related patent
US 2019/0392287 A1Published application
US 11,775,802 B2This patent

From the US filing history. Foreign family members aren’t listed.