Integrated circuit having latch-up immunity
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Fang Lai, Guan-Yu Chen, Yi-Feng Chang
Life of this patent
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Abstract
An integrated circuit includes a semiconductor substrate, devices, first tap regions, and second tap regions. The devices are over the semiconductor substrate. The first tap regions are over the semiconductor substrate along a first direction. The second tap regions are over the semiconductor substrate along the first direction. A first pitch between adjacent two of the first tap regions in the first direction is greater than a second pitch between adjacent two of the second tap regions in the first direction.
Claims20
An integrated circuit, comprising:
- a semiconductor substrate;
- a plurality of devices over the semiconductor substrate;
- a plurality of first tap regions in the semiconductor substrate and arranged along a first direction;
- a plurality of second tap regions in the semiconductor substrate and arranged along the first direction, wherein a first pitch between adjacent two of the first tap regions in the first direction is greater than a second pitch between adjacent two of the second tap regions in the first direction;
- and
- a plurality of third tap regions in the semiconductor substrate and arranged along the first direction, wherein the third tap regions are adjacent to the first tap regions and have an opposite conductive type to the first tap regions, and a third pitch between adjacent two of the third tap regions in the first direction is substantially equal to the first pitch between said adjacent two of the first tap regions in the first direction.
An integrated circuit, comprising:
- a semiconductor substrate comprising a first well and a second well;
- a first tap region, a second tap region, and a third tap region in the first well and arranged along a first direction in a sequence;
- a fourth tap region and a fifth tap region in the second well and arranged along the first direction;
- a plurality of first devices over the first well, wherein a first portion of the first devices are between the first and second tap regions, and a second portion of the first devices are between the second and third tap regions;
- and
- a plurality of second devices over the second well and between the fourth and fifth tap regions, wherein the second tap region is aligned with one of the second devices along a second direction perpendicular to the first direction.
An integrated circuit, comprising:
- a semiconductor substrate comprising a first well and a second well;
- a first tap region and a second tap region in the first well, wherein the first and second tap regions are spaced apart from each other by a first distance along a first direction;
- a plurality of first devices over the first well and between the first and second tap regions from a top view;
- a third tap region and a fourth tap region in the second well, wherein the third and fourth tap regions are spaced apart from each other by a second distance along the first direction, and the second distance is less than the first distance;
- and
- a plurality of second devices over the second well and between the third and fourth tap regions from the top view.
Dependencies are inferred from the claim text.