Systems and methods for obfuscating a circuit design

A system comprising:

• a processor configured to:
• receive a plurality of electrical parameters of a system on chip (SoC) to be designed, wherein the plurality of electrical parameters are received on a data sheet;
• receive a plurality of physical parameters of the SoC on the data sheet;
• generate a first design of the SoC based on the plurality of electrical parameters and the plurality of physical parameters;
• receive a plurality of test parameters for testing the first design;
• test, using a design verification tool, the first design by applying the plurality of test parameters to the first design;
• receive a second design of a second SoC;
• couple the second design to the first design to generate a first integrated circuit (IC) chip design;
• and
• arrange the first IC chip design to be included on a shuttle for fabricating a first IC chip;
• and
• a memory device coupled to the processor.

A method for generating an integrated circuit (IC) chip design, comprising:

• receiving, by a client device, a plurality of electrical parameters of a first system on chip (SoC) to be designed;
• receiving a plurality of physical parameters of the first SoC;
• generating a first design of the first SoC according to the plurality of physical parameters and the plurality of electrical parameters;
• receiving a plurality of test parameters for testing the first design;
• providing the plurality of test parameters via a computer network to a server for applying the plurality of test parameters to test the first design;
• coupling a second design of a second SoC to the first design to generate a first IC chip design;
• and
• providing the first IC chip design to be included on a shuttle for fabricating a first IC chip.