Integrated circuit development using machine learning-based prediction of power, performance, and area
AssigneeInternational Business Machines Corporation
InventorsTuhin Mahmud, Saiful Islam, Abraham Mathews, Geoffrey Wang
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Abstract
Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.
Claims20
A computer-implemented method comprising:
- obtaining, using a processor, values that define an architecture design of a memory array, the feature values comprising a bit count, an entry count, a number of read ports, and a number of write ports for the memory array;
- building a correlation matrix comprising the feature values and a plurality of power, performance, and area (PPA) components from prior memory arrays;
- identifying, using the correlation matrix, one or more features of the feature values that most strongly correlated with the PPA components;
- training a machine learning model to obtain a predicted PPA of the memory array on the identified one or more features;
- and
- assessing the predicted PPA output by the machine learning model based on predefined PPA goals, wherein a design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.
A system comprising:
- a memory having computer readable instructions;
- and
- one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
- obtaining feature values that define an architecture design of a memory array, the feature values comprising a bit count, an entry count, a number of read ports, and a number of write ports for the memory array;
- building a correlation matrix comprising the feature values and a plurality of power, performance, and area (PPA) components from prior memory arrays;
- identifying, using the correlation matrix, one or more features of the feature values that most strongly correlated with the PPA components;
- training a machine learning model to obtain a predicted PPA of the memory array on the identified one or more features;
- and
- assessing the predicted PPA output by the machine learning model based on predefined PPA goals, wherein a design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
- obtaining feature values that define an architecture design of a memory array, the feature values comprising a bit count, an entry count, a number of read ports, and a number of write ports for the memory array;
- building a correlation matrix comprising the feature values and a plurality of power, performance, and area (PPA) components from prior memory arrays;
- identifying, using the correlation matrix, one or more features of the feature values that most strongly correlated with the PPA components;
- training a machine learning model to obtain a predicted PPA of the memory array on the identified one or more features;
- and
- assessing the predicted PPA output by the machine learning model based on predefined PPA goals, wherein a design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.
Dependencies are inferred from the claim text.