Methods and apparatus to simulate metastability for circuit design verification
AssigneeTexas Instruments Incorporated
InventorsSudhakar Surendran, Venkatraman Ramakrishnan
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Abstract
Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
Claims20
A method comprising:
- inserting metastability logic into a simulation model during a simulation of a circuit design, wherein the metastability logic includes a set of parallel delay paths;
- and
- simulating operation of the circuit design based on the simulation model that includes the metastability logic.
A non-transitory computer readable medium comprising instructions that, when executed by at least one processor of a computing system, cause the computing system to at least:
- insert metastability logic into a simulation model, wherein the metastability logic includes a set of delay paths, wherein each delay path of the set of delay paths has a different delay;
- and
- simulate operation of a circuit design based on the simulation model including the metastability logic.
An apparatus comprising:
- a simulator to simulate operation of a circuit design based on a simulation model;
- a metastability injector to insert metastability logic that includes a synchronizer that includes a set of selectable delay paths into the simulation model during simulation of the circuit design;
- and
- a metastability controller to control the metastability logic during the simulation of the circuit design.
Dependencies are inferred from the claim text.