High speed, low hardware footprint waveform
AssigneeSynopsys, Inc.
InventorsArturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
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Abstract
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
Claims17
A method of capturing signals during simulation or emulation of a circuit design using at least one field-programmable gate array (FPGA), the method comprising:
- selecting, at run time, a plurality of signals, one signal at a time, to be captured using one or more pre-compiled macros;
- storing values associated with the selected plurality of signals in a memory disposed in the at least one FPGA;
- storing the values associated with each of the selected signals during cycles of a sequencer;
- comparing a first value of a first signal stored during a cycle of the sequencer to a second value of the first signal stored during a preceding cycle of the sequencer;
- inhibiting output transfer of the first value of the first signal if the second value of the first signal is equal to the first value of the first signal;
- and
- transferring one of the first or second values of the first signal to an output data stream.
A system configured to capture signals during simulation or emulation of a circuit design using at least one field-programmable gate array (FPGA), the system comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- select, at run time, a plurality of signals, one signal at a time, to be captured using one or more pre-compiled macros;
- store values associated with the selected plurality of signals in a memory disposed in the at least one FPGA;
- and
- store the value associated with a first one of the selected plurality of signals in the memory at an address generated by a sequencer.
A non-transitory computer readable medium comprising stored instructions, the stored instructions when executed by a processor, cause the processor to capture signals during simulation or emulation of a circuit design using at least one field-programmable gate array (FPGA), the stored instructions further causing the processor to:
- select, at run time, a plurality of signals, one signal at a time, to be captured using one or more pre-compiled macros;
- and
- store values associated with the selected plurality of signals in a memory disposed in the at least one FPGA;
- and
- store the value associated with a first one of the selected plurality of signals in the memory at an address generated by a sequencer.
Dependencies are inferred from the claim text.