US 11,775,693 B1 · Hardware trojan detection using path delay based side-channel analysis and reinforcement learning

Abstract

The present disclosure describes systems and methods for test pattern generation to detect a hardware Trojan using delay-based analysis. One such method comprises determining a set of initial test patterns to activate the hardware Trojan within an integrated circuit design; and generating a set of succeeding test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model. The set of initial test patterns can be applied as an input to the reinforcement learning model. Further, the reinforcement learning model can be trained with a stochastic learning scheme to increase a probability of triggering one or more rare nodes in the integrated circuit design and identify optimal test vectors to maximize delay-based side-channel sensitivity when the hardware Trojan is activated in the integrated circuit design. Other methods and systems are also provided.

Claims20

Dependent claims

A method for test pattern generation to detect a hardware Trojan using delay-based analysis comprising:

determining, by a computing device, a set of initial test patterns to activate the hardware Trojan within an integrated circuit design;
and
generating, by the computing device, a set of succeeding test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model, wherein the set of initial test patterns is applied as an input to the reinforcement learning model, wherein the reinforcement learning model is trained with a stochastic learning scheme to increase a probability of triggering one or more rare nodes in the integrated circuit design and identify optimal test vectors to maximize delay-based side-channel sensitivity when the hardware Trojan is activated in the integrated circuit design.

A system for test pattern generation to detect a hardware Trojan using delay-based analysis, the system comprising:

a processor of a computing device;
and
a tangible, non-transitory memory configured to communicate with the processor, the tangible, non-transitory memory having instructions stored thereon that, in response to execution by the processor, cause the computing device to at least:
determine a set of initial test patterns to activate the hardware Trojan within an integrated circuit design;
and
generate a set of succeeding test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model, wherein the set of initial test patterns is applied as an input to the reinforcement learning model, wherein the reinforcement learning model is trained with a stochastic learning scheme to increase a probability of triggering one or more rare nodes in the integrated circuit design and identify optimal test vectors to maximize delay-based side-channel sensitivity when the hardware Trojan is activated in the integrated circuit design.

3 more elements

Dependencies are inferred from the claim text.

Hardware trojan detection using path delay based side-channel analysis and reinforcement learning

Life of this patent

Hardware trojan detection using path delay based side-channel analysis and reinforcement learning

Life of this patent

Abstract

Claims20