Autonomous detection of cache-based side-channel attacks
AssigneeNEC Corporation
InventorsJianyu Jiang, Ghassan Karame, Claudio Soriente
Life of this patent
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Abstract
A method for detecting a cache-based side-channel attack includes utilizing a timer thread that continuously increments a variable in code of an application. The code has been instrumented such that the instrumented code uses the variable incremented by the timer thread to infer an amount of time taken for running a part of the code. A number of cache misses during execution of the part of the code is determined based on the amount of time. It is determined whether the application is experiencing the cache-based side-channel attack using a classifier which uses as input the number of cache misses.
Claims20
A method for detecting a cache-based side-channel attack, the method comprising:
- utilizing a timer thread that continuously increments a variable in code of an application that has been instrumented such that the instrumented code uses the variable incremented by the timer thread to infer an amount of time taken for running a part of the code;
- determining a number of cache misses during execution of the part of the code based on the amount of time;
- and
- determining whether the application is experiencing the cache-based side-channel attack using a classifier which uses as input the number of cache misses.
A system comprising one or more processors which, alone or in combination, are configured to provide for execution of a method comprising:
- utilizing a timer thread that continuously increments a variable in code of an application that has been instrumented such that the instrumented code uses the variable incremented by the timer thread to infer an amount of time taken for running a part of the code;
- determining a number of cache misses during execution of the part of the code based on the amount of time;
- and
- determining whether the application is experiencing the cache-based side-channel attack using a classifier which uses as input the number of cache misses.
A tangible, non-transitory computer-readable medium having instructions thereon which, upon being executed by one or more processors, alone or in combination, provide for execution of a method comprising:
- utilizing a timer thread that continuously increments a variable in code of an application that has been instrumented such that the instrumented code uses the variable incremented by the timer thread to infer an amount of time taken for running a part of the code;
- determining a number of cache misses during execution of the part of the code based on the amount of time;
- and
- determining whether the application is experiencing the cache-based side-channel attack using a classifier which uses as input the number of cache misses.
Dependencies are inferred from the claim text.