Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof

A method for generating an output sequence for performing on-chip testing by using pseudo-random binary sequence (PRBS) generator, comprising:

• providing a plurality of lanes consisting of a combination of at least flip flops selected in a range of 6-14, 2 latches, and 7 logic gates, wherein
• each lane comprises a latch group configured for receiving clock signals, and wherein
• a number of latches in each latch group is based on the output sequence to be generated for performing the on-chip testing;
• and
• connecting each of the latch group having at least the flip flops selected in the range of 6-14 and a latch of one of the 2 latches or the flip flops selected in the range of 6-14 with a plurality of logic gates of the 7 logic gates in such a manner that an output, generated by the at least the flip-flops selected in the range of 6-14 and the latch of each of the latch group, is provided as an input to the plurality of logic gates for generating the output sequence required for performing the on-chip testing.