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US 11,770,937 B2Granted
Magnetic memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHan-Na Cho, Bok-Yeon Won, Oik Kwon
Life of this patent
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Abstract
A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.
Claims20
A magnetic memory device, comprising:
- a substrate including a cell region and a peripheral circuit region;
- lower contact plugs on the cell region;
- data storage structures on the lower contact plugs;
- and
- a peripheral interconnection structure on the peripheral circuit region,
- wherein the peripheral interconnection structure includes
- a line portion on the peripheral circuit region, and
- a contact portion extending from the line portion toward the substrate,
- wherein a height of the contact portion is less than a height of each of the lower contact plugs.
6 more elements
A magnetic memory device, comprising:
- a substrate including a cell region and a peripheral circuit region;
- an etch stop layer on the cell region and the peripheral circuit region;
- a lower interlayer insulating layer on the etch stop layer;
- a data storage structure on the lower interlayer insulating layer on the cell region;
- an upper interlayer insulating layer on the cell region and the peripheral circuit region;
- a protective insulating layer between a sidewall of the data storage structure and the upper interlayer insulating layer;
- and
- a peripheral interconnection structure penetrating the upper interlayer insulating layer and the lower interlayer insulating layer on the peripheral circuit region,
- wherein the peripheral interconnection structure includes
- a line portion extending in a horizontal direction parallel to a top surface of the substrate, and
- a contact portion extending from the line portion toward the substrate,
- wherein the contact portion extending from the line portion toward the substrate,
- wherein the lower interlayer insulating layer and the upper interlayer insulating layer on the cell region respective have recessed top surfaces,
- wherein a distance between a top surface of the lower interlayer insulating layer and a top surface of the upper interlayer insulating layer on the peripheral circuit region is less than a maximum value of a distance between the recessed top surface of the lower interlayer insulating layer and the recessed top surface of the upper interlayer insulating layer on the cell region.
11 more elements
A magnetic memory device, comprising:
- a substrate including a cell region and a peripheral circuit region;
- a lower interlayer insulating layer on the cell region and the peripheral circuit region;
- a data storage structure on the lower interlayer insulating layer on the cell region;
- an upper interlayer insulating layer on the cell region and the peripheral circuit region;
- a protective insulating layer between a sidewall of the data storage structure and the upper interlayer insulating layer and between a top surface of the lower interlayer insulating layer and the upper interlayer insulating layer on the cell region;
- and
- a peripheral interconnection structure penetrating the upper interlayer insulating layer and the lower interlayer insulating layer on the peripheral circuit region,
- wherein the peripheral interconnection structure includes
- a line portion extending in a horizontal direction parallel to a top surface of the substrate, and
- a contact portion extending from the line portion toward the substrate,
- wherein a thickness of the lower interlayer insulating layer adjacent to the data storage structure is thicker than a thickness of the lower interlayer insulating layer adjacent to the peripheral interconnection structure,
- wherein a ratio of a height of the contact portion to a width of a bottom surface of the contact portion is equal to or less than 1.5:1.
9 more elements
Dependencies are inferred from the claim text.