Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell

A apparatus comprising:

• a transistor, the transistor having a source region and a drain region, and a gate;
• a first via is coupled to the source region;
• a second via is coupled to the drain region;
• a first metal layer over the first via, the first metal layer that extends along an x-plane;
• a second etch stop layer over the first metal layer;
• a third via over the first metal layer, the third via coupled to the first metal layer;
• a second metal layer that extends along the x-plane, wherein the second metal layer is above the first metal layer, wherein the second metal layer couples the third via;
• an interlayer dielectric between the first metal layer and the second metal layer;
• a first pedestal filled with a first metal, wherein the first pedestal is coupled to the second metal layer;
• a first plurality of layers to form a first planar capacitor, wherein the first plurality of layers includes non-linear polar material, and wherein a first layer of the first plurality of layers is in contact with a top portion of the first pedestal;
• a fourth via coupled to the second metal layer;
• a third metal layer over the fourth via, wherein the first plurality of layers is between the second metal layer and the third metal layer;
• a second pedestal filled with a second metal, wherein the second pedestal is coupled to the third metal layer;
• and
• a second plurality of layers to form a second planar capacitor, wherein the second plurality of layers includes a linear dielectric material, and wherein a first layer of the second plurality of layers is coupled with a top portion of the second pedestal.

A system comprising:

• a memory to store one or more instructions on the memory;
• a processor circuitry to execute the one or more instructions;
• and
• a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
• a first metal layer that extends along an x-plane;
• a second metal layer that extends along the x-plane, wherein the second metal layer is above the first metal layer;
• a first via extending along a y-plane, wherein the y-plane is orthogonal to the x-plane, wherein the first via couples the first metal layer with the second metal layer;
• a second via that extends along the y-plane, wherein the second via couples the second metal layer, wherein the second via is above the first via;
• a first pedestal on the first metal layer, wherein the first pedestal is laterally offset from the first via;
• a second pedestal on the second metal layer, wherein the second pedestal is laterally offset from the second via;
• a first plate-line that extends along a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane;
• a second plate-line that extends along the z-plane;
• a first planar stack of materials including a non-linear polar material, wherein the first planar stack of materials has a first top electrode and a first bottom electrode, wherein the non-linear polar material is between the first top electrode and the first bottom electrode, wherein the first bottom electrode is on the first pedestal, and wherein the first plate-line is on the first top electrode;
• and
• a second planar stack of materials including a linear dielectric material, and wherein the second planar stack of materials has a second top electrode and a second bottom electrode, wherein the linear dielectric material is between the second top electrode of the second planar stack of materials and the second bottom electrode of the second planar stack of materials, wherein the second bottom electrode is on the second pedestal, and wherein the second plate-line on the second top electrode.