Semiconductor structure and method of fabricating the same

A semiconductor structure, comprising:

• a bottom interconnection array, comprising a first word line driver and an auxiliary word line driver spaced apart from one another in a first direction;
• a memory device disposed above the bottom interconnection array, wherein the memory device comprises:
• an array region disposed on the bottom interconnection array and partially overlapped with the first word line driver;
• a first staircase region disposed on the first word line driver and surrounded by the array region, wherein the first staircase region comprises mirror image steps;
• a sub-array region disposed on the bottom interconnection array and partially overlapped with the auxiliary word line driver;
• an auxiliary staircase region disposed on the auxiliary word line driver and surrounded by the sub-array region, wherein the auxiliary staircase region comprises mirror image steps;
• conductive bridge structures disposed on the first word line driver and the auxiliary word line driver, wherein the conductive bridge structures extend along the first direction and are electrically connected to the mirror image steps of the first staircase region and the mirror image steps of the auxiliary staircase region;
• and
• conductive routings, extending from the mirror image steps of the first staircase region to the first word line driver, and extending from the mirror image steps of the auxiliary staircase region to the auxiliary word line driver.

A method of fabricating a semiconductor structure, comprising:

• providing a word line driver over a semiconductor substrate;
• forming a first portion of routings electrically connected to the word line driver;
• forming a multilayer stack over the word line driver and over the first portion of routings;
• patterning the multilayer stack to form a memory array and a staircase unit, wherein the memory array is disposed in an array region of the semiconductor structure and comprises a plurality of word lines, and the staircase unit is disposed in a staircase region of the semiconductor structure and surrounded by the array region, wherein the staircase unit comprises first staircase steps and second staircase steps extending from the plurality of word lines of the memory array, and the first staircase steps and the second staircase steps face towards each other, and wherein the word line driver is disposed below the memory array and the staircase unit, and a central portion of the word line driver is overlapped with a central portion of the staircase unit;
• forming a plurality of conductive bridge structures connecting the first staircase steps to the second staircase steps, wherein each of the plurality of conductive bridge structures are extending from one step of the first staircase steps to one step of the second staircase steps in a horizontal direction, and wherein each of the plurality of conductive bridge structures extending in the horizontal direction are physically separated from one another and are arranged in parallel to one another;
• forming a plurality of dielectric layers extending from the first staircase steps to the second staircase steps in the horizontal direction, wherein each of the plurality of dielectric layers are separated from one another by the plurality of conductive bridge structures;
• and
• forming a second portion of routings electrically connected to the first portion of routings and the stair case unit, wherein conductive routings constituted by the first portion of routings and the second portion of routings are extending from the first staircase steps and the second staircase steps towards the word line driver, and the plurality of dielectric layers cover and physically contact top surfaces of the conductive routings.