Memory device including row decoder

A memory device comprising:

• is a substrate, defined with a first plane region and a second plane region that are disposed in a first direction, and each of the first plane region and the second plane region includes a cell region and a row decoder region adjacent to the cell region in the first direction;
• a plurality of pass transistors defined in the row decoder regions of the first plane region and the second plane region of the substrate;
• a peripheral circuit defined in the cell regions of the first plane region and of the second plane region of the substrate;
• a plurality of bottom wiring layers disposed in a first dielectric layer that covers the pass transistors and the peripheral circuit;
• a memory cell array of a first plane, which is disposed on the first dielectric layer and is provided in the cell region of the first plane region, and a memory cell array of a second plane, which is disposed on the first dielectric layer and is provided in the cell region of the second plane region;
• a second dielectric layer defined on the first dielectric layer and covering the memory cell arrays;
• a plurality of top wiring layers disposed in a third dielectric layer, which is defined on the second dielectric layer;
• and
• a plurality of global lines disposed in the row decoder regions of the first plane region and the second plane region and configured to transfer operating voltages to the plurality of pass transistors,
• wherein the plurality of global lines are disposed only in at least one bottom wiring layer among the plurality of bottom wiring layers and the plurality of top wiring layers.