Methods of forming microelectronic devices

A method of forming a microelectronic device, comprising:

• forming a microelectronic device structure comprising:
• a stack structure comprising conductive material and insulative material vertically alternating with the conductive material;
• a conductive lateral contact structure vertically neighboring the stack structure;
• cell pillar structures vertically extending through the stack structure and the conductive lateral contact structure, the cell pillar structures individually comprising:
• an outer material stack having an outer sidewall in physical contact with the stack structure;
• and
• channel material having an outer side surface in physical contact each of the conductive lateral contact structure and an inner sidewall of the outer material stack;
• a conductive deep contact structure vertically extending through the stack structure and coupled to the conductive lateral contact structure;
• and
• conductive line structures vertically neighboring the stack structure and coupled to the cell pillar structures;
• forming an additional microelectronic device structure comprising complementary-metal-oxide-semiconductor (CMOS) circuitry;
• bonding the microelectronic device structure to the additional microelectronic device structure to form an assembly including the conductive line structures vertically between the stack structure and the CMOS circuitry;
• and
• forming a high work function (HWF) metal material in physical contact with the channel material of the cell pillar structures after bonding the microelectronic device structure to the additional microelectronic device structure.

A method of forming a microelectronic device, comprising:

• forming a first structure having control logic devices comprising complementary-metal-oxide-semiconductor (CMOS) circuitry;
• forming a second structure comprising:
• a base structure;
• doped polycrystalline silicon comprising at least one P-type dopant overlying the base structure;
• additional doped polycrystalline silicon comprising at least one N-type dopant overlying the doped polycrystalline silicon;
• a stack structure overlying the additional doped polycrystalline silicon and comprising tiers individually including conductive material vertically adjacent insulative material;
• pillars vertically extending through the stack structure and the additional doped polycrystalline silicon into the doped polycrystalline silicon, the pillars individually comprising:
• channel material comprising semiconductor material;
• and
• an outer stack structure horizontally surrounding the channel material;
• and
• conductive line structures overlying the stack structure and coupled to the pillars;
• bonding dielectric oxide material of the first structure to additional dielectric oxide material of the second structure to form an assembly including the conductive line structures vertically interposed between the stack structure and the control logic devices;
• subjecting the assembly to at least one material removal process to remove the base structure, at least some of the doped polycrystalline silicon, and portions of and the outer stack structure of each of the pillars;
• and
• forming an active body structure comprising a metal material having a work function greater than or equal to about 4.7 electronvolts in physical contact with the channel material of the pillars after subjecting the assembly to the at least one material removal process, junctions between the channel material of the pillars and the metal material of the active body structure forming Schottky contacts.