Vertical memory devices with segmented charge storage layers

A semiconductor device, comprising:

• gate layers vertically stacked on a substrate and spaced apart from each other;
• interlayer insulating layers alternately stacked with the gate layers on the substrate;
• and
• channel structures with channel holes, respectively, penetrating the gate layers and extending perpendicularly to the substrate, each channel structure including first dielectric layers, first electric charge storage layers, a second dielectric layer, and a channel layer stacked sequentially from side surfaces of the gate layers in a respective channel hole,
• wherein the first dielectric layers and the first electric charge storage layers are separated from each other between adjacent ones of the gate layers,
• wherein the first dielectric layers are on the side surfaces of the gate layers, such that the first dielectric layers do not extend to or contact side surfaces of the interlayer insulating layers, the side surfaces of the interlayer insulating layers facing a same direction as the side surfaces of the gate layers, and the first dielectric layers have rounded surfaces protruding and curved toward the channel layer, respectively, and
• wherein the first electric charge storage layers are on the rounded surfaces of the first dielectric layers.

A semiconductor device, comprising:

• gate layers vertically stacked on a substrate and spaced apart from each other;
• interlayer insulating layers alternately stacked with the gate layers on the substrate;
• a channel layer penetrating the gate layers and extending perpendicularly to an upper surface of the substrate;
• first dielectric layers on side surfaces of the gate layers, respectively, between the gate layers and the channel layer;
• electric charge storage layers on side surfaces of the first dielectric layers, respectively, between the first dielectric layers and the channel layer;
• and
• a second dielectric layer between the electric charge storage layers and the channel layer, the second dielectric layer being in contact with side surfaces of the interlayer insulating layers between the gate layers vertically adjacent to each other.