Semiconductor device with trench structure to reduce parasitic capacitance and leakage current

A semiconductor device comprising:

• a semiconductor substrate including an element isolation layer, an active region, and a trench, the active region defined by the element isolation layer and arranged in a first direction, and the trench formed in a part of the element isolation layer and the active region;
• a plurality of buried contacts connected to the active region and arranged in a second direction different from the first direction;
• a direct contact in the trench, the direct contact having a width smaller than a width of the trench, and the direct contact being connected to the active region;
• a plurality of bit line structures connected to the semiconductor substrate through the direct contact, the plurality of bit lines structures extending in a third direction across the active region between at least two buried contacts of the plurality of the buried contacts;
• and
• a spacer structure extending in the third direction along side surfaces of the plurality of bit line structures,
• wherein the spacer structure includes a first spacer, a second spacer, a third spacer, and an air spacer, the first spacer extending along a side surface of the direct contact and the trench, the second spacer on the first spacer and filling a remaining portion of the trench, the third spacer including a vertical portion and a horizontal portion, the vertical portion extending along a side surface of the bit line structure and the horizontal portion extending along a top surface of the second spacer, and the air spacer on the third spacer and spaced apart from the second spacer by the vertical portion of the third spacer, and
• the first spacer including silicon oxide.

A semiconductor device comprising:

• a semiconductor substrate including a gate trench;
• at least one gate electrode filling at least a part of the gate trench and extending in a first direction;
• at least one source/drain region on a side surface of the at least one gate electrode;
• a plurality of buried contacts electrically connected to the at least one source/drain region, the plurality of buried contacts being arranged in the first direction;
• at least one landing pad on the at least one buried contact;
• at least one capacitor structure on the at least one landing pad and electrically connected to the at least one landing pad and the at least one buried contact;
• at least one bit line structure extending in a second direction between at least two of the plurality of buried contacts, the at least one bit structure including a conductive pattern and a capping pattern on the conductive pattern;
• and
• a spacer structure on a side surface of the at least one bit line structure and extending in the second direction,
• wherein the spacer structure includes,
• a first spacer extending along a lower side surface of the bit line structure,
• a second spacer on the first spacer,
• a third spacer extending along an upper side surface of the bit line structure, a top surface of the first spacer, and a top surface of the second spacer,
• an air spacer above the second spacer and the third spacer, the air spacer spaced apart from the second spacer by the third spacer,
• a fourth spacer on the second spacer and the air spacer on the top surface of the first spacer,
• the first spacer including silicon oxide, and
• the second to fourth spacers including silicon nitride.