Analog-to-digital converter for an image sensor

An analog-to-digital converter for an image sensor, comprising:

• a counter circuit having a counter control connection to apply a clock signal and a plurality of counter output connections to generate a respective counter bit in response to a counter state of the counter circuit,
• a storage circuit comprising a plurality of storage cells, wherein a respective one of the storage cells is connected to a respective one of the counter output connections for storing a respective storage state in response the respective counter bit,
• a comparator circuit for generating a level of a comparison signal in response to a comparison of an input signal and a reference signal,
• a synchronization circuit to apply the comparison signal and the clock signal and to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell,
• a latch circuit to generate a delayed write control signal,
• wherein the counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter control connection of the counter circuit,
• wherein the synchronization circuit is configured to generate the write control signal in response to a level of the comparison signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit,
• wherein the counter circuit comprises a first counter circuit portion and at least a second counter circuit portion,
• wherein the first counter circuit portion has a first portion of the counter output connections, the first counter circuit portion being configured to generate a respective Least Significant Bit at a respective counter output connection of the first portion of the counter output connections,
• wherein the second counter circuit portion has a second portion of the counter output connections, the second counter circuit portion being configured to generate a respective Most Significant Bit at a respective counter output connection of the second portion of the counter output connections,
• wherein the latch circuit is connected to the synchronization circuit so that the write control signal is applied to a respective one of the storage cells connected to a respective one of the first portion of the counter output connections, and the delayed write control signal is applied to a respective one of the storage cells connected to a respective one of the second portion of the counter output connections.