Reconfigurable analog-to-digital converter
AssigneeSenseics Corporation
InventorRamy S. Tantawy
Life of this patent
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Abstract
An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.
Claims20
An integrated circuit (IC), comprising:
- an analog to digital converter (ADC) circuit comprising an ADC input and an ADC output,
- wherein the ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal,
- wherein an ADC circuit path is coupled between the ADC input and the ADC output,
- wherein the ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path,
- wherein the ADC has a reconfigurable resolution and a reconfigurable sampling rate,
- wherein the ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.
An integrated circuit (IC), comprising:
- an analog to digital converter (ADC) circuit comprising an ADC input and an ADC output, wherein the ADC circuit is configured to receive an input signal at the ADC input, wherein the ADC circuit is configured to generate a digital output signal based on the input signal, and wherein the ADC circuit comprises:
- a comparator circuit having a comparator input coupled to the ADC input and a comparator output;
- a plurality of capacitor digital-to-analog converters (CDACs) having first terminals coupled between the ADC input and the comparator input;
- a successive-approximation-register (SAR) logic circuit having a logic input coupled to the comparator output and logic outputs;
- a multiplexer circuit having multiplexer inputs coupled to the logic outputs and a multiplexer output corresponding to the ADC output;
- and
- wherein the ADC circuit is configured to adjust a CDAC capacitive loading of the plurality of CDACs based on an adjustable resolution of the ADC circuit.
An integrated circuit (IC), comprising:
- an analog to digital converter (ADC) circuit comprising an ADC input configured to receive an input signal, wherein the ADC circuit is configured to generate an output signal based on the input signal, wherein the ADC has a monotonic switching successive approximation register (SAR) ADC architecture that is configured to trigger a first comparison generating a most significant bit (MSB) of the output signal when the input signal is sampled, wherein a self-initiated binary search of successive approximation logic asynchronously generates remaining ADC bits, and wherein the ADC circuit has a reconfigurable resolution, a reconfigurable sampling rate, and a reconfigurable power consumption.
Dependencies are inferred from the claim text.