Receiver with half-rate sampler circuits

A method comprising:

• generating, using a front-end circuit, a filtered signal based on a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
• combining, using a summing circuit, the filtered signal and an analog signal that is based on a digital feedback signal to generate an equalized signal;
• generating, using a first sampler circuit to sample the equalized signal during a first time period, a first regeneration signal;
• generating, using a second sampler circuit to sample the equalized signal during a second time period, a second regeneration signal;
• generating, using a compensation circuit, the digital feedback signal based on the first regeneration signal and the second regeneration signal;
• generating an analog feedback signal, using digital-to-analog converter (DAC) circuitry;
• canceling, using the first sampler circuit during the first time period, first inter-symbol interference in the equalized signal using the second regeneration signal;
• and
• canceling, using the second sampler circuit during the second time period, second inter-symbol interference in the equalized signal using the first regeneration signal.

A system comprising:

• a first sampler circuit configured to sample an equalized data signal and further configured to generate a first regenerated data signal;
• a second sampler circuit configured to sample the equalized data signal and further configured to generate a second regenerated data signal, wherein the first and second samplers are configured to alternately sample the equalized data signal over consecutive time periods;
• a feedback circuit configured to generate a digital feedback signal based on the first and second regenerated data signals;
• and
• a summing circuit configured to generate the equalized data signal based on a filtered signal and an analog feedback signal generated based on the digital feedback signal wherein the filtered signal is generated by a front-end circuit based on a plurality of signals that encode a serial data stream that includes a plurality of data symbols,
• wherein the first and second sampler circuits are configured to alternately cancel inter-symbol interference using the second and first regenerated data signals, respectively, during alternating time periods.