Hardware accelerator for Feistel block ciphers
AssigneeNordic Semiconductor ASA
InventorMatti Tiikkainen
Life of this patent
Estimating the term…
Abstract
A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.
Claims14
A hardware accelerator for performing cipher operations to convert between a plaintext message and a ciphertext message, the hardware accelerator comprising:
- a first memory area arranged to store a first bit string provided at an input thereto;
- a second memory area arranged to store a second bit string provided at an input thereto;
- a calculation block arranged to receive a round key and to perform a function on the first bit string, wherein the function comprises combining the first bit string with the round key to produce a combined bit string, and performing a non-linear mapping from the combined bit string to a mapped bit string;
- an addition block arranged to add the mapped bit string to the second bit string to produce a resultant bit string;
- and
- a controller arranged to receive a control signal, wherein the controller is further arranged such that:
- when the control signal is in a first state, the controller provides the resultant bit string to the input of the first memory area and provides the first bit string to the input of the second memory area;
- and
- when the control signal is in a second state, the controller provides the first bit string to the input of the first memory area and provides the resultant bit string to the input of the second memory area.
A method of operating a hardware accelerator for performing cipher operations to convert between a plaintext message and a ciphertext message, the hardware accelerator comprising first and second memory areas, wherein the method comprises:
- storing a first bit string in the first memory area, wherein the first bit string is provided at an input to said first memory area;
- storing a second bit string in the second memory area, wherein the second bit string is provided at an input to said second memory area;
- receiving a round key;
- performing a function on the first bit string, wherein the function comprises combining the first bit string with the round key to produce a combined bit string, and performing a non-linear mapping from the combined bit string to a mapped bit string;
- adding the mapped bit string to the second bit string to produce a resultant bit string;
- and
- receiving a control signal;
- when the control signal is in a first state, providing the resultant bit string to the input of the first memory area and providing the first bit string to the input of the second memory area;
- and
- when the control signal is in a second state, providing the first bit string to the input of the first memory area and providing the resultant bit string to the input of the second memory area.
Dependencies are inferred from the claim text.