Mixed-signal dot product processor with single capacitor per multiplier

A method for forming a mixed-signal logic processor, comprising:

• forming a dot product computation portion by arranging a plurality of mixed-signal multiplier branches to each have a set of branch-dedicated switches and a single branch-dedicated capacitor, each of the plurality of mixed-signal multiplier branches connected to a single common node and each branch having a different voltage level, and the set comprising two switches connected in parallel, wherein the dot product computation portion further comprises:
• connecting a common switch external to each of the plurality of mixed-signal multiplier branches;
• and
• positioning the common switch between a first shared branch-external capacitor and a second shared branch-external capacitor such that only the first shared branch-external capacitor directly connects to the common single node connecting all of the plurality of mixed-signal multiplier branches;
• wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor comprising a reset mode, a sample mode, a merge mode, and an accumulate mode for a dot product computation.

A computer processing system, comprising:

• a mixed-signal logic processor, wherein the mixed-signal logic processor comprises:
• a dot product computation portion having a plurality of mixed-signal multiplier branches, each of the plurality of mixed-signal multiplier branches connected to a single common node, and each of the plurality of mixed-signal multiplier branches having a set of branch-dedicated switches and a single branch-dedicated capacitor where each branch has a different voltage level, the set including two switches connected in parallel, wherein the dot product computation portion further comprises:
• a common switch being external to each of the plurality of mixed-signal multiplier branches;
• and
• a first shared branch-external capacitor and a second shared branch-external capacitor positioned on opposed ends of the common switch, the first and the second shared branch-external capacitors being external to each of the plurality of mixed-signal multiplier branches such that only the first shared branch-external capacitor directly connects to the single common node connecting all of the plurality of mixed-signal multiplier branches,
• wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor comprising a reset mode, a sample mode, a merge mode, and an accumulate mode for a dot product computation.