Duty cycle correction for high-speed clock signals

Clock circuitry, comprising:

• reference clock circuitry configured to output a reference clock at an output of the reference clock circuitry;
• a frequency divider, having an input coupled to the output of the reference clock circuitry and configured to generate, at an output of the frequency divider, an input clock signal having a frequency divided down from the frequency of the reference clock by an odd-valued integer;
• a duty cycle correction circuit, having an input coupled to the output of the frequency divider and configured to output an output clock signal at an output of the duty cycle correction circuit;
• and
• at least one clock generator circuit, having an input coupled to the output of the duty cycle correction circuit, the at least one clock generator circuit configured to generate one or more clock signals based on the output clock signal from the duty cycle correction circuit;
• wherein the duty cycle correction circuit comprises:
• a circuit input receiving the input clock signal;
• a delay stage, having a first input operable to receive the reference clock and a second input coupled to the circuit input, the delay stage configured to output, at an output of the delay stage, a delayed clock signal corresponding to the input clock signal delayed by one half-cycle of the reference clock;
• a logic circuit, having a first input coupled to the circuit input and a second input coupled to the output of the delay stage, the logic circuit configured to output, at an output of the logic circuit, an extended clock signal corresponding to a logical OR of the input clock signal and the delayed clock signal;
• a latch circuit, having an input coupled to the output of the logic circuit and an enable input operable to receive the reference clock, the latch circuit configured to latch the state of the extended clock signal when enabled by the reference clock, and to output its latched state at an output of the latch circuit;
• a flip-flop, having a data input coupled to the output of the logic circuit, and a clock input operable to receive the reference clock, the flip-flop configured to latch the state at its data input responsive to a selected transition of the reference clock and to output its latched state at an output of the flip-flop;
• a gate circuit configured to selectively couple, to an output of the gate circuit, a selected one of the output of the latch and the output of the flip-flop responsive to a state of the delayed clock signal;
• and
• a multiplexer, having a first input coupled to the circuit input, a second input coupled to the output of the gate circuit, a select input operable to receive the reference clock, and an output coupled to the output of the duty cycle correction circuit, the multiplexer configured to select its first and second inputs, in alternating phases of the reference clock, for application at the output of the multiplexer.

A duty cycle correction method, comprising:

• receiving an input clock signal having a frequency divided down from the frequency of a reference clock by an odd-valued integer,
• delaying the input clock signal by a half-cycle of the reference clock to produce a delayed signal;
• combining the input clock signal with the delayed signal to produce an extended clock signal;
• latching, by a latch circuit, the extended clock signal during a first phase of the reference clock, and outputting a latched state of the latch circuit during a second phase of the reference clock;
• latching, by an edge-triggered flip-flop, the extended clock signal responsive to a transition of the reference clock to the first phase, and outputting a latched state of the flip-flop until a next transition of the reference clock to the first phase;
• generating an intermediate signal by alternately selecting between the output of the latch circuit and the output of the flip-flop;
• and
• generating an output clock using the intermediate signal.