Dynamic enhancement of loop response upon recovery from fault conditions

An apparatus comprising:

• a fault detector configured to detect a fault condition in response to an input voltage of a Pulse Width Modulation (PWM) converter falling below a programmed output voltage of the PWM converter;
• a sampling circuit connected to a fault detector output of the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to a current sense output of a current sensor configured to sense a sensed current conducted through a transistor, wherein the sampling circuit samples a peak voltage at the end of at least one of a plurality of clock cycles of the PWM converter, and the peak voltage is proportional to the sensed current;
• and
• an offset circuit connected between a sampling output of the sampling circuit and an error output of an error amplifier, wherein the offset circuit is configured to preset the error output to an error value determined by the peak voltage, a PWM driver configured to drive the transistor in response to the error value, and the transistor configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.

A method for dynamic enhancement of loop response upon recovery from fault conditions comprising:

• detecting a fault condition in response to a feedback voltage input of a Pulse Width Modulation (PWM) converter decreasing below a programmed output voltage of the PWM converter;
• sampling a peak voltage at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor;
• presetting an error output of an error amplifier to an error value determined by the peak voltage, controlling a PWM driver with the error value to drive the transistor;
• and
• charging an output load to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

An apparatus comprising:

• a fault detector configured to detect a fault condition in response to a feedback voltage input of a Pulse Width Modulation (PWM) converter falling below a programmed output voltage of the PWM converter;
• a sampling circuit connected to a fault detector output of the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to a current sense output of a current sensor configured to sense a sensed current conducted through a transistor, wherein the sampling circuit samples a peak voltage at the end of at least one of a plurality of clock cycles of the PWM converter, and the peak voltage is proportional to the sensed current;
• and
• an offset circuit connected between a sampling output of the sampling circuit and an error output of an error amplifier, wherein the offset circuit is configured to preset the error output to an error value determined by the peak voltage, a PWM driver configured to drive the transistor in response to the error value, and the transistor configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.

A method for dynamic enhancement of loop response upon recovery from fault conditions comprising:

• detecting a current limit fault condition by comparing a sensed current conducted through a transistor with a current limit value;
• sampling a peak voltage at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the current limit fault condition, wherein the peak voltage is proportional to the sensed current conducted through the transistor;
• presetting an error output of an error amplifier to an error value determined by the peak voltage, controlling a PWM driver with the error value to drive the transistor;
• and
• charging an output load to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

An apparatus comprising:

• a fault detector configured to detect a current limit fault condition by comparing a sensed current conducted through a transistor with a current limit value;
• a sampling circuit connected to a fault detector output of the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to the current sense output of a current sensor configured to sense the sensed current conducted through the transistor, wherein the sampling circuit samples a peak voltage at the end of at least one of a plurality of clock cycles of the PWM converter, and the peak voltage is proportional to the sensed current;
• and
• an offset circuit connected between a sampling output of the sampling circuit and an error output of an error amplifier, wherein the offset circuit is configured to preset the error output to an error value determined by the peak voltage, a PWM driver configured to drive the transistor in response to the error value, and the transistor configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.