Gate-all-around integrated circuit structures having nanowires with tight vertical spacing

An integrated circuit structure, comprising:

• a vertical arrangement of horizontal silicon nanowires, wherein one or more of the silicon nanowires comprises a coating comprising carbon;
• a gate stack around the vertical arrangement of horizontal silicon nanowires, the gate stack having a bottommost surface beneath the vertical arrangement of horizontal silicon nanowires;
• a first source or drain structure at a first end of the vertical arrangement of horizontal silicon nanowires, the first source or drain structure having a bottommost surface above the bottommost surface of the gate stack;
• and
• a second source or drain structure at a second end of the vertical arrangement of horizontal silicon nanowires, the second source or drain structure having a bottommost surface above the bottommost surface of the gate stack.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a vertical arrangement of horizontal silicon nanowires, wherein a vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers, and wherein one or more of the silicon nanowires comprises a coating comprising carbon;
• a gate stack around the vertical arrangement of horizontal silicon nanowires, the gate stack having a bottommost surface beneath the vertical arrangement of horizontal silicon nanowires;
• a first source or drain structure at a first end of the vertical arrangement of horizontal silicon nanowires, the first source or drain structure having a bottommost surface above the bottommost surface of the gate stack;
• and
• a second source or drain structure at a second end of the vertical arrangement of horizontal silicon nanowires, the second source or drain structure having a bottommost surface above the bottommost surface of the gate stack.