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US 11,769,832 B2Granted
Memory device comprising an electrically floating body transistor and methods of using
AssigneeZeno Semiconductor, Inc.
InventorsJin-Woo Han, Dinesh Maheshwari, Yuniarto Widjaja
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Abstract
A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
Claims24
A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells include:
- a memory transistor comprising a bi-stable floating body transistor having a first body region, wherein said first body region comprises a floating body region;
- and
- a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;
- and
- an access device comprising a second body region;
- wherein said bi-stable floating body transistor and said access device are electrically connected in series;
- wherein said bi-stable floating body transistor further comprises a first gate region connected to a first terminal;
- wherein said access device further comprises a second gate region connected to a second terminal;
- wherein said access device further comprises a bit line region connected to a third terminal;
- wherein a first voltage level applied to said first terminal during write operations to both said first and second states is about the same;
- wherein a second voltage level applied to said second terminal during said write operations to both said first and second states is about the same;
- wherein there is a time delay between when said first voltage level is triggered and when said second voltage level is triggered;
- and
- wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.
12 more elements
An integrated circuit comprising:
- a semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a memory transistor comprising a bi-stable floating body transistor having a first body region, wherein said first body region comprises a floating body region;
- and
- a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;
- and
- an access device comprising a second body region;
- wherein said bi-stable floating body transistor and said access device are electrically connected in series;
- wherein said bi-stable floating body transistor further comprises a first gate region connected to a first terminal;
- wherein said access device further comprises a second gate region connected to a second terminal;
- wherein said access device further comprises a bit line region connected to a third terminal;
- wherein a first voltage level applied to said first terminal during write operations to both said first and second states is about the same;
- wherein a second voltage level applied to said second terminal during said write operations to both said first and second states is about the same;
- wherein there is a time delay between when said first voltage level is triggered and when said second voltage level is triggered;
- wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells;
- and
- a control circuit controlling an operation of said semiconductor memory array.
14 more elements
Dependencies are inferred from the claim text.