US 11,769,831 B2 · High performance floating body VFET with dielectric core

Abstract

Aspects of the present disclosure provide a floating body vertical field effect transistor with dielectric core and a method for fabricating the same. The floating body vertical field effect transistor can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures and can include a second semiconductor device formed on the same substrate adjacent to the first semiconductor device; a salicide layer or doped layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The floating body vertical field effect transistor may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.

Claims20

Dependent claims

A device, comprising:

a first stack of epitaxially grown semiconductor material extending perpendicular to a working surface of a substrate, the first stack of epitaxially grown semiconductor material wrapping around a first dielectric material structure extending perpendicular to the working surface of a substrate, the first stack of epitaxially grown semiconductor material including a layer of intrinsic semiconductor material in between layers of doped semiconductor material, a bottom layer of the first stack of epitaxially grown semiconductor material forming a first source/drain, the layer of intrinsic semiconductor material being a channel of a first field effect transistor, and the upper layer of the first stack of epitaxially grown semiconductor material forming a second source/drain;
and
a second stack extending perpendicular to the working surface and positioned in a plane with the first stack of epitaxially grown semiconductor material, the second stack wrapping around the first stack of epitaxially grown semiconductor material, the second stack having a first metal layer positioned in between layers of dielectric material, the first metal layer forming a gate of the first field effect transistor.

A semiconductor device, comprising:

a P-type substrate including a PMOS field effect transistor adjacent an NMOS field effect transistor, the P-type substrate including:
a dielectric diffusion break configured to electrically isolate the PMOS field effect transistor from the NMOS field effect transistor;
a background doped N-type region;
the PMOS field effect transistor including:
a first stack of epitaxially grown semiconductor material located over a P-type implant region of the P-type substrate and extending perpendicular to a working surface of a substrate, the first stack wrapping around a first dielectric material structure, the first stack of epitaxially grown semiconductor material including a first layer of intrinsic semiconductor material in between layers of P+ doped semiconductor material, a bottom layer of the first stack forming a first source/drain, the first layer of intrinsic semiconductor material being a channel of the PMOS field effect transistor, and the upper layer of the first stack forming a second source/drain;
a second stack extending perpendicular to the working surface positioned in plane with the first stack and wrapping around the first stack, the second stack having a first metal layer formed of Metal 2 material, the first metal layer positioned in between layers of dielectric material, the first metal layer forming a gate of PMOS field effect transistor;
wherein the first layer of intrinsic semiconductor material is at a same plane as the first metal layer;
the NMOS field effect transistor including:
a third stack of epitaxially grown semiconductor material extending perpendicular to a working surface of the P-type substrate, the third stack wrapping around a second dielectric material structure, the third stack of epitaxially grown semiconductor material including a second layer of intrinsic semiconductor material in between layers of N+ doped semiconductor material, a bottom layer of the third stack forming a third source/drain, the second layer of intrinsic semiconductor material being a channel of the NMOS field effect transistor, and the upper layer of the third stack forming a fourth source/drain;
a fourth stack extending perpendicular to the working surface of the P-type substrate, positioned in plane with the third stack and wrapping around the third stack, the fourth stack having a second metal layer of Metal 1 material positioned in between layers of dielectric material, the second metal layer forming a gate of the second field effect transistor;
wherein the second layer of intrinsic semiconductor material is at a same plane as the second metal layer;
a first high-K layer formed between the first stack and the second stack;
and
a second high-K layer formed between the third stack and the fourth stack.

11 more elements

A method of microfabrication of a semiconductor device, the method comprising:

epitaxially growing a first stack of semiconductor material extending perpendicular to a working surface of a substrate, the first stack wrapping around a first dielectric material structure, the first stack including a first layer of intrinsic semiconductor material in between layers of doped semiconductor material, a bottom layer of the first stack forming a first source/drain, the first layer of intrinsic semiconductor material being a channel of a first field effect transistor, and an upper layer of the first stack forming a second source/drain;
depositing a second stack extending perpendicular to the working surface positioned in plane with the first stack and wrapping around the first stack, the second stack having a first metal layer positioned in between layers of dielectric material and at a same plane as the first layer of intrinsic semiconductor material, the first metal layer forming a gate of the first field effect transistor;
forming a high-K layer between the first stack and the second stack;
and
implanting a doped region located along the working surface of the substrate beneath the first stack and the second stack.

2 more elements

Dependencies are inferred from the claim text.

High performance floating body VFET with dielectric core

Life of this patent

High performance floating body VFET with dielectric core

Life of this patent

Abstract

Claims20