Semiconductor device with asymmetric gate structure

A semiconductor device, comprising:

• a channel layer;
• a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG) along an interface between the channel layer and the barrier layer;
• a source contact and a drain contact positioned above the barrier layer;
• a doped group III-V layer positioned above the barrier layer and between the drain contact and the source contact, wherein the first doped group III-V layer has a first left sidewall and a first right sidewall which are curved and opposite each other;
• and
• a gate electrode positioned above the doped group III-V layer and having a second left sidewall and a second right sidewall which are curved and opposite each other, wherein a horizontal distance from the first left sidewall to the second left sidewall is different than a horizontal distance from the first right sidewall to the second right sidewall, and a surface roughness of the second left sidewall is substantially different from a surface roughness of the second right sidewall.

A semiconductor device, comprising:

• a channel layer;
• a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG) along an interface between the channel layer and the barrier layer;
• a low voltage device comprising:
• a first source contact and a first drain contact which are positioned above the barrier layer;
• a first doped group III-V layer positioned above the barrier layer and between the first drain contact and the first source contact;
• and
• a first gate electrode positioned above the first doped group III-V layer and having a first sidewall adjacent to the first source contact and a second sidewall adjacent to the first drain contact, wherein a profile of the first sidewall and a profile of the second sidewall are substantially in non-specular symmetry with respect to a geometric center of the first doped group III-V layer;
• and a surface roughness of the first sidewall is substantially different from a surface roughness of the second sidewall;
• and
• a high voltage device comprising:
• a second source contact and a second drain contact which are positioned above the barrier layer;
• a second doped group III-V layer positioned above the barrier layer and between the second drain contact and the second source contact;
• and
• a second gate electrode positioned above the second doped group III-V layer and having a third sidewall adjacent to the second source contact and a fourth sidewall adjacent to the second drain contact, wherein a profile of the third sidewall and a profile of the fourth sidewall are substantially in non-specular symmetry with respect to a geometric center of the second doped group III-V layer, and a surface roughness of the third sidewall is substantially different from a surface roughness of the fourth sidewall.