Gallium nitride transistor with a doped region
AssigneeTexas Instruments Incorporated
InventorsDong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
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Abstract
In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
Claims22
A method for fabricating a transistor, comprising:
- forming a heterostructure over a substrate, the heterostructure including a gallium nitride (GaN) layer, and a GaN-based alloy layer disposed on the GaN layer and having a top side;
- implanting dopants directly to the top side of the GaN-based alloy layer to form a doped region extending from the top side into the GaN layer in a drain access region;
- and
- depositing source, drain, and gate contact structures that are supported by the GaN layer.
A method for fabricating a transistor on a substrate including a gallium nitride (GaN) layer and a GaN-based alloy layer disposed on the GaN layer, comprising:
- implanting dopants directly to a top side of the GaN-based alloy layer to form a doped region extending through the GaN-based alloy layer into the GaN layer in a drain access region;
- and
- forming source, drain, and gate contact structures that are supported by the GaN layer, wherein:
- the drain contact structure has a first edge nearest the gate contact structure and a second edge opposite the first edge;
- the doped region has a first edge nearest the gate contact structure and a second edge opposite the first edge;
- and
- the second edge of the doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure such that the drain contact structure extends past the doped region.
A method for fabricating a transistor, comprising:
- obtaining a substrate including a gallium nitride (GaN) layer, a GaN-based alloy layer disposed on the GaN layer and having a top side;
- implanting dopants to form a doped region extending from the top side into the GaN layer in a drain access region while blocking the dopants from a source region and a gate region of the transistor;
- and
- depositing source, drain, and gate contact structures that are supported by the GaN layer, wherein the drain contact structure at least partially contacts the doped region.
A method for fabricating a transistor on a substrate including a gallium nitride (GaN) layer and a GaN-based alloy layer disposed on the GaN layer, comprising:
- implanting dopants to form a doped region extending through the GaN-based alloy layer into the GaN layer in a drain access region;
- and
- forming source, drain, and gate contact structures that are supported by the GaN layer, wherein:
- the drain contact structure has a first edge nearest the gate contact structure and a second edge opposite the first edge;
- the doped region has a first edge nearest the gate contact structure and a second edge opposite the first edge;
- the second edge of the doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure such that the drain contact structure extends past the doped region;
- and
- the drain contact structure at least partially contacts the doped region.
Dependencies are inferred from the claim text.