Field effect transistors with negative capacitance layers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChansyun David Yang, Chan-Lon Yang, Keh-Jeng Chang
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Abstract
The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.
Claims20
A semiconductor device, comprising:
- a stack of semiconductor layers on a substrate, wherein the stack of semiconductor layers comprises a first semiconductor layer on the substrate and a second semiconductor layer adjacent to the first semiconductor layer;
- first and second gate dielectric layers wrapped around the first and second semiconductor layers, respectively, wherein the first and second gate dielectric layers comprise a negative capacitance (NC) dielectric material;
- and
- an NC layer between the first and second gate dielectric layers, wherein the NC layer comprises the NC dielectric material.
A semiconductor device, comprising:
- first and second semiconductor layers on a substrate, wherein the second semiconductor layer is adjacent to the first semiconductor layer;
- first and second gate dielectric layers wrapped around the first and second semiconductor layers, respectively;
- a negative capacitance (NC) layer between the first and second gate dielectric layers, wherein the NC layer comprises an NC dielectric material;
- and
- an inner spacer structure in contact with the NC layer, wherein a portion of the inner spacer structure extends into the NC layer.
A method, comprising:
- forming a stack of semiconductor layers on a substrate, wherein the stack of semiconductor layers comprises a first semiconductor layer on the substrate, a sacrificial semiconductor layer on the first semiconductor layer, and a second semiconductor layer on the sacrificial semiconductor layer;
- removing a first region of the sacrificial semiconductor layer;
- filling the first region with a first negative capacitance (NC) dielectric structure, wherein the first NC dielectric structure comprises an NC dielectric material;
- removing a second region of the sacrificial semiconductor layer, wherein the second region is in contact with the first region;
- and
- filling the second region with a second NC dielectric structure, wherein the second NC dielectric structure is in contact with the first NC dielectric structure.
Dependencies are inferred from the claim text.