Carrier barrier layer for tuning a threshold voltage of a ferroelectric memory device

A method for forming an integrated circuit (IC) chip comprising:

• forming a gate electrode, a ferroelectric structure, and a semiconductor structure vertically stacked over a substrate with the ferroelectric structure between the semiconductor structure and the gate electrode;
• depositing a dielectric layer over the semiconductor structure;
• etching the dielectric layer to form a pair of openings respectively on opposite sides of the gate electrode;
• depositing a carrier barrier layer lining and partially filling the pair of openings;
• and
• forming a pair of source/drain electrodes directly on the carrier barrier layer, respectively at the pair of openings.

A method for forming a memory cell, comprising:

• forming a multilayer stack over a substrate, wherein the multilayer stack comprises a semiconductor layer and a ferroelectric layer;
• forming a gate electrode, wherein the ferroelectric layer is directly between the gate electrode and the semiconductor layer upon completion of the forming of the multilayer stack and the gate electrode;
• forming a first carrier barrier structure and a second carrier barrier structure directly contacting the semiconductor layer respectively on opposite sides of the gate electrode;
• and
• forming a source electrode and a drain electrode respectively overlying and directly contacting the first and second carrier barrier structures;
• wherein the first carrier barrier structure comprises semiconductor material configured to shift an OFF voltage of the memory cell towards zero and forms a Schottky barrier with the source electrode.