Semiconductor device including gate structure and separation structure

A semiconductor device, comprising:

• a first active fin and a second active fin disposed on a substrate;
• an insulating layer disposed between the first active fin and the second active fin and on the substrate;
• first active layers on the first active fin, the first active layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate;
• second active layers on the second active fin, the second active layers being spaced apart from each other in the vertical direction;
• a first gate structure intersecting the first active layers and extending in a first direction, the first gate structure surrounding each of the first active layers;
• a second gate structure intersecting the second active layers and extending in the first direction, the second gate structure surrounding each of the second active layers;
• and
• a separation structure disposed between first gate structure and the second gate structure, and extending into the insulating layer,
• wherein the first gate structure has a first end portion disposed on the insulating layer;
• wherein the second gate structure has a second end portion facing the first end portion of the first gate structure in the first direction,
• wherein the separation structure contacts the first end portion of the first gate structure, the second end portion of the second gate structure, and the insulating layer,
• wherein the separation structure includes a lower portion contacting the insulating layer, an intermediate portion on the lower portion, and an upper portion on the intermediate portion,
• a maximum width of the intermediate portion of the separation structure in the first direction is greater than a maximum width of the lower portion of the separation structure in the first direction, and
• the maximum width of the intermediate portion of the separation structure in the first direction is greater than a maximum width of the upper portion of the separation structure in the first direction,
• wherein the first gate structure includes a first gate dielectric structure and a first gate electrode structure on the first gate dielectric structure,
• wherein the second gate structure includes a second gate dielectric structure and a second gate electrode structure on the second gate dielectric structure,
• wherein the intermediate portion of the separation structure includes a first portion vertically overlapping the first gate electrode structure and a second portion vertically overlapping the second gate electrode structure,
• wherein a first boundary between a side wall of the intermediate portion and a side wall of the upper portion is at a higher level than a lower surface of the first gate electrode structure, and is at a lower level than an upper surface of the first gate electrode structure, and
• wherein a second boundary between the side wall of the intermediate portion and a side wall of the lower portion is at a higher level than a lower surface of the insulating layer, and is at a lower level than an upper surface of the insulating layer.

A semiconductor device, comprising:

• a substrate;
• an active fin and an insulating layer on the substrate;
• a first source/drain region and a second source/drain region on the active fin and spaced apart from each other;
• active layers between the first source/drain region and the second source/drain region, the active layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate;
• a gate structure intersecting the active layers and extending in a first direction, the gate structure surrounding each of the active layers;
• and
• a separation structure on the insulating layer and contacting the gate structure,
• wherein the gate structure has an end portion on the insulating layer,
• wherein the separation structure contacts the insulating layer and the end portion of the gate structure,
• wherein the gate structure includes a gate dielectric structure and a gate electrode structure on the gate dielectric structure,
• wherein the gate dielectric structure contacts the active layers,
• wherein the separation structure includes a side wall extending into the insulating layer and being in contact with the end portion of the gate structure,
• wherein the side wall of the separation structure includes a lower side wall, a first side wall on the lower side wall, a second side wall on the first side wall, and an upper side wall on the second side wall,
• wherein an inclination of the lower side wall is greater than an inclination of the first side wall with respect to a boundary surface between the gate structure and the insulating layer,
• wherein the first side wall includes a portion in contact with the insulating layer,
• wherein the second side wall includes a portion in contact with the gate electrode structure, and
• wherein a portion of the separation structure defined between the first side wall and the second side wall overlaps the gate electrode structure in a plan view.