Structures of gate contact formation for vertical transistors

An array comprising:

• a plurality of vertical transistors, each comprising;
• a semiconductor pillar standing over a substrate;
• a gate dielectric disposed over at least a portion of said semiconductor pillar;
• and
• a gate surrounding a middle portion of said semiconductor pillar over said gate dielectric;
• extended gate regions;
• and wherein:
• said array comprises at least one row;
• each of said at least one row has at least one of said extended gate regions;
• each of said at least one of said extended gate regions in each of said at least one row extends horizontally from a bottom edge, but not from a top edge, of said gate of at least one of said plurality of vertical transistors in each of said at least one row;
• a space between said semiconductor pillars of immediate neighbors of said plurality of vertical transistors in each of said at least one row is sufficiently narrow and said gate film is sufficiently thick such that said plurality of vertical transistors are coupled at said gate along each of said at least one row;
• and
• where said plurality of semiconductor pillars are arranged in said array with at least two rows, a space between said at least two rows is sufficiently wide and said gate film is sufficiently thin such that said plurality of vertical transistors are disconnected at said gate between said at least two rows.

An array comprising:

• a plurality of vertical transistors, each comprising:
• a semiconductor pillar standing over a substrate;
• a gate dielectric disposed over at least a portion of said semiconductor pillar;
• and
• a gate surrounding a middle portion of said semiconductor pillar over said gate dielectric;
• a dielectric film covering said substrate up to bottom surface of said extended gate regions and surrounding a bottom portion of said semiconductor pillar of each of said plurality of vertical transistors;
• extended gate regions;
• and wherein:
• said array comprises at least one row;
• each of said extended gate regions is disposed in a middle position of each of said at least one row;
• a space between immediate neighbors of semiconductor pillars of said plurality of vertical transistors is sufficiently narrow except at said middle position and said gate is sufficiently thick such that said plurality of vertical transistors are coupled at said gate except at said middle position;
• where said plurality of semiconductor pillars are arranged in said array with at least two rows, a space between said at least two rows is sufficiently wide and said gate film is sufficiently thin such that said plurality of vertical transistors are disconnected at said gate between said at least two rows;
• and
• each of said extended gate regions in each of said at least one row extends horizontally from a bottom edge, but not from a top edge, of said gate of each of two of said plurality of transistors next to said middle position in each of said at least one row.

A semiconductor device comprising:

• a semiconductor substrate containing an electric circuitry formed therein;
• interconnect metal lines disposed in said substrate and coupled to said electric circuitry;
• a plurality of vertical transistors formed over said substrate;
• a gate formed vertically for each said vertical transistors;
• and
• extended gate regions extending horizontally from bottom edges, but not from top edges, of said gates of select some of said vertical transistors such that each of said select some of said vertical transistors has only one of said extended gate regions extending from said gate.