Method of manufacturing semiconductor device and associated memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNuo Xu, Zhiqiang Wu
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Abstract
A method includes providing a substrate including a channel region, the substrate comprising a two-stage structure having a first surface, a second surface higher than the first surface and a third surface connected between the first surface and the second surface; covering the substrate from a top thereof with an oxide layer; forming a ferroelectric material strip on a topmost surface of the oxide layer; and forming a gate strip covering the ferroelectric material strip and the oxide layer from a top of the gate strip.
Claims20
A method of manufacturing a semiconductor device, comprising:
- providing a substrate including a channel region, the substrate comprising a two-stage structure having a first surface, a second surface higher than the first surface and a third surface connected between the first surface and the second surface;
- covering the substrate from a top thereof with an oxide layer;
- forming a ferroelectric material strip on a topmost surface of the oxide layer;
- and
- forming a gate strip covering the ferroelectric material strip and the oxide layer from a top of the gate strip.
A method of manufacturing a semiconductor device, comprising:
- providing a substrate;
- forming a gate electrode layer on the substrate;
- generating a trench on the gate electrode layer to expose a top surface of the substrate;
- covering a part of a sidewall of the trench with a ferroelectric material layer;
- and
- covering rest portions of the sidewall of the trench and the ferroelectric material layer with an oxide layer.
A memory device, comprising:
- a plurality of memory cells connected in series, each of the plurality of memory cells including a first transistor, a second transistor and a capacitor, wherein the first transistor and the second transistor are connected in parallel, and the capacitor is connected to gate terminals of the first transistor and the second transistor;
- and
- a selection transistor connected to one end of the plurality of memory cells in series.
Dependencies are inferred from the claim text.