High capacitance MIM device with self aligned spacer

A method of forming a capacitor structure, comprising:

• forming one or more lower interconnects within a lower dielectric structure over a substrate;
• forming a first dielectric layer over the lower dielectric structure;
• forming a plurality of openings extending through the first dielectric layer to expose the one or more lower interconnects;
• forming a capacitor stack over the first dielectric layer and within the plurality of openings, the capacitor stack comprising a capacitor dielectric layer between a lower electrode layer and an upper electrode layer;
• forming one or more capping layers over the upper electrode layer;
• etching the one or more capping layers and the upper electrode layer to define a capping structure over an upper electrode;
• forming a spacer along sidewalls of the capping structure and the upper electrode, wherein the spacer has an outermost surface that extends from the capacitor dielectric layer to a top of the spacer;
• and
• etching the capacitor dielectric layer and the lower electrode layer according to the spacer to define a capacitor dielectric over a lower electrode.

A method of forming a capacitor structure, comprising:

• forming an opening within a first dielectric over a substrate;
• forming a capacitor stack over the first dielectric and within the opening, the capacitor stack comprising a capacitor dielectric layer between a lower electrode layer and an upper electrode layer;
• patterning the upper electrode layer according to one or more masking layers to form an upper electrode;
• forming a spacer along sidewalls of the upper electrode and the one or more masking layers, wherein the capacitor dielectric layer has a horizontally extending surface that extends from directly below the spacer to laterally outside of the spacer;
• etching the capacitor dielectric layer and the lower electrode layer according to the spacer and the one or more masking layers to form a capacitor dielectric over a lower electrode;
• forming a first photoresist onto the one or more masking layers;
• etching the one or more masking layers according to the first photoresist prior to patterning the upper electrode layer;
• forming a second photoresist onto the spacer after patterning the upper electrode layer;
• and
• etching the spacer according to the second photoresist.