Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors

A device structure comprising:

• a conductive interconnect within a first dielectric in a first level;
• and
• a second level above the first level, the second level comprising:
• an electrode structure on the conductive interconnect;
• an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
• a second dielectric on the etch stop layer;
• a trench within the second dielectric, the trench on the electrode structure;
• and
• a memory device within the trench, the memory device comprising:
• a conductive barrier layer along a base and a sidewall of the trench and in contact with the electrode structure;
• a first electrode adjacent to the conductive barrier layer, the first electrode comprising a first conductive nonlinear polar material, wherein the first conductive nonlinear polar material comprises a first grain length;
• a dielectric layer comprising a perovskite material on the first electrode and substantially conformal to the first electrode, the perovskite material comprising a second grain length;
• and
• a second electrode in contact with the dielectric layer, the second electrode comprising a second conductive nonlinear polar material on the dielectric layer, the second conductive nonlinear polar material comprising a third grain length less than or equal to the first grain length or the second grain length;
• a via electrode on the second electrode, the via electrode comprising:
• a conductive hydrogen barrier electrode comprising a lateral portion in contact with the second electrode, and substantially vertical portions connected to the lateral portion;
• and
• a second conductive fill material adjacent to the conductive hydrogen barrier electrode.

A system comprising:

• a processor comprising a transistor;
• a communication interface communicatively coupled to the processor;
• and
• a memory coupled to the transistor, wherein the memory comprises:
• bit-cells, wherein one of the bit-cells comprises:
• a conductive interconnect within a first dielectric in a first level;
• and
• a second level above the first level, the second level comprising:
• an electrode structure on the conductive interconnect, the electrode structure comprising:
• a first conductive fill material;
• a first conductive hydrogen barrier electrode on the first conductive fill material;
• and
• an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
• a second dielectric on the etch stop layer;
• a trench within the second dielectric, the trench on the electrode structure;
• a memory device within the trench, the memory device comprising:
• a first electrode along a base and a sidewall of the trench, the first electrode comprising a first conductive nonlinear polar material, the first conductive nonlinear polar material comprising a first grain length and wherein the first electrode is in contact with the electrode structure;
• a dielectric layer comprising a perovskite material on the first electrode and substantially conformal to the first electrode, the perovskite material comprising a second grain length;
• and
• a second electrode in contact with the dielectric layer, the second electrode comprising a second conductive nonlinear polar material on the dielectric layer, the second conductive nonlinear polar material comprising a third grain length less than or equal to the first grain length or the second grain length;
• a via electrode on the second electrode, the via electrode comprising:
• a second conductive hydrogen barrier electrode comprising a lateral portion in contact with the second electrode and substantially vertical portions connected to the lateral portion;
• and
• a second conductive fill material adjacent to the second conductive hydrogen barrier electrode.