Thin film transistor array substrate for digital X-ray detector device and digital X-ray detector device and manufacturing method thereof

A thin film transistor array substrate for a digital X-ray detector device, comprising:

• a base substrate;
• a thin film transistor disposed over the base substrate;
• a PIN (P type semiconductor-Intrinsic type semiconductor-N type semiconductor) diode configured to be connected to the thin film transistor, the PIN diode including a lower electrode, a PIN layer, and an upper electrode;
• and
• a leakage current blocking layer configured to cover a side surface of the PIN layer and contact the PIN layer,
• wherein the leakage current blocking layer includes metal.

A digital X-ray detector device, comprising:

• a base substrate;
• a thin film transistor disposed over the base substrate;
• a PIN (P type semiconductor-Intrinsic type semiconductor-N type semiconductor) diode configured to be connected to the thin film transistor, the PIN diode including a lower electrode, a PIN layer, and an upper electrode;
• and
• a leakage current blocking layer configured to cover a side surface of the PIN layer and contact the PIN layer;
• an insulating layer covering the side surface of the leakage current blocking layer;
• and
• a scintillator layer disposed over the PIN layer,
• wherein the leakage current blocking layer is disposed between the PIN layer and the insulating layer and the leakage current blocking layer is made of material that is different from material that the insulating layer is made of, and the leakage current blocking layer is made of material not including silicon, and
• wherein the leakage current blocking layer does not contact the upper electrode.

A digital X-ray detector device, comprising:

• a base substrate;
• a thin film transistor disposed over the base substrate;
• a PIN (P type semiconductor-Intrinsic type semiconductor-N type semiconductor) diode configured to be connected to the thin film transistor, the PIN diode including a lower electrode, a PIN layer, and an upper electrode;
• a leakage current blocking layer configured to cover a side surface of the PIN layer and contact the PIN layer;
• and
• a scintillator layer disposed over the PIN layer,
• wherein the leakage current blocking layer includes metal.