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US 11,769,762 B2Granted
Semiconductor package and stacked package module including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDaeho Lee, Kilsoo Kim
Life of this patent
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Abstract
A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.
Claims20
A semiconductor package comprising:
- a lower redistribution layer including a plurality of lower ball pads forming N lower ball pad groups, N being an integer greater than or equal to two;
- a semiconductor chip on the lower redistribution layer;
- an expanded layer surrounding the semiconductor chip on the lower redistribution layer;
- an upper redistribution layer on the semiconductor chip and the expanded layer, the upper redistribution layer including a plurality of upper ball pads forming M upper ball pad groups, M being an integer equal to N,
- the M upper ball pad groups including a dummy upper ball pad group and remaining upper ball pad groups,
- the dummy upper ball pad group being defined by each of the plurality of upper ball pads in one of the M upper ball pad groups;
- a chip-lower portion electrical connection path electrically connecting a one of the N lower ball pad groups to the semiconductor chip;
- and
- an upper portion-lower portion electrical connection path connecting the remaining lower ball pad groups to remaining upper ball pad groups, the N lower ball pad groups including the one of the N lower ball pad groups and the remaining lower ball pad groups.
6 more elements
A stacked package module comprising:
- a plurality of semiconductor packages,
- the plurality of semiconductor packages including a first semiconductor package and a second semiconductor package stacked on the first semiconductor package,
- each of the plurality of semiconductor packages including a lower redistribution layer, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, an upper redistribution layer on the semiconductor chip and the expanded layer, and a first upper portion-lower portion electrical connection path,
- the lower redistribution layer including a plurality of lower ball pads forming a plurality of lower ball pad groups, the plurality of lower ball pad groups including a first lower ball pad group and a second lower ball pad group,
- the upper redistribution layer including a plurality of upper ball pads forming a plurality of upper ball pad groups, the plurality of upper ball pad groups including a first upper ball pad group and a second upper ball pad group,
- the first lower ball pad group and the first upper ball pad group being electrically connected through the first upper portion-lower portion electrical connection path, and
- each of the upper ball pads in the second upper ball pad group, from among the plurality of upper ball pads, being a dummy ball pad.
4 more elements
A stacked package module comprising:
- a first semiconductor package, a second semiconductor package, a third semiconductor package, a fourth semiconductor package which are stacked sequentially,
- each of the first semiconductor package, the second semiconductor package, the third semiconductor package, and the fourth semiconductor package including a lower redistribution layer, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, an upper redistribution layer on the semiconductor chip and the expanded layer, a first upper portion-lower portion electrical connection path, a second upper portion-lower portion electrical connection path, a chip-lower portion electrical connection path, and a third upper portion-lower portion electrical connection path,
- the lower redistribution layer including a plurality lower ball pads forming a plurality of lower ball pad groups,
- the plurality of lower ball pad groups including a first lower ball pad group, a second lower ball pad group, a third lower ball pad group, and a fourth lower ball pad group,
- the upper redistribution layer including a plurality of upper ball pads forming a plurality of upper ball pad groups,
- the plurality of upper ball pad groups including a first upper ball pad group, a second upper ball pad group, a third upper ball pad group, and a fourth upper ball pad group,
- the first lower ball pad group and the first upper ball pad group being electrically connected through the first upper portion-lower portion electrical connection path,
- the second lower ball pad group and the second upper ball pad group being electrically connected through the second upper portion-lower portion electrical connection path,
- the third lower ball pad group and the semiconductor chip being electrically connected through the chip-lower portion electrical connection path,
- the fourth lower ball pad group and the third upper ball pad group being electrically connected through the third upper portion-lower portion electrical connection path, and
- each of the upper ball pads forming the fourth upper ball pad group, from among the plurality of upper ball pads, being a dummy ball pad.
8 more elements
Dependencies are inferred from the claim text.