Thermally-optimized tunable stack in cavity package-on-package
AssigneeIntel Corporation
InventorsGeorge Vakanas, Aastha Uppal, Shereen Elhalawaty, Aaron McCann, Edvin Cetegen, Tannaz Harirchian, Saikumar Jayaraman
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Abstract
Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
Claims11
An electronics package, comprising:
- a package substrate;
- a first die coupled to the package substrate, the first die having a bottommost surface above an uppermost surface of an entirety of the package substrate;
- a second die over the first die, wherein the first die and the second die are electrically coupled to the package substrate with wire bonds;
- a cavity through the package substrate, wherein the cavity is within a footprint of the first die;
- and
- a thermal stack in the cavity, wherein the thermal stack directly physically contacts the first die, and wherein the thermal stack is within the footprint of the first die.
Dependencies are inferred from the claim text.