Back to results
US 11,769,737 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJunghoon Han, Jongmin Lee
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorsJunghoon Han, Jongmin Lee
Estimating the term…
A semiconductor package includes an upper conductive pattern and a redistribution layer on a first surface of a substrate, a semiconductor chip facing the first surface of the substrate, the semiconductor chip being spaced apart from the first surface of the substrate, a conductive bump bonding between the semiconductor chip and the upper conductive pattern, the conductive bump electrically connecting the semiconductor chip and the upper conductive pattern, and an upper passivation layer on the redistribution layer, a portion of the upper passivation layer facing an edge of a lower surface of the semiconductor chip.
A semiconductor package, comprising:
A semiconductor package, comprising:
A semiconductor package, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Arrangements for protection of devices: protecting against mechanical damage
Package substrates; Interposers; Redistribution layers [RDL]: connecting interconnections to insulating or insulated package substrates,…
Characterised by their interconnections: shapes or dispositions of interconnections
Characterised by their insulating layers or insulating parts: shapes or dispositions thereof
About 14 years 7 months of term left · ends 13 May 2041 (estimated)
Korean Patent Application No. 10-2020-0131737, filed on Oct. 13, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Package,” is incorporated by reference herein in its entirety.
Example embodiments relate to a semiconductor package. Particularly, example embodiments relate to a semiconductor package including a semiconductor chip bonded on an interposer substrate.
A semiconductor package may include a package substrate, an interposer substrate, a semiconductor chip, and conductive bumps. The semiconductor chip may be bonded on a first surface of the interposer substrate.
Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
FIG. 1 is a cross-sectional view of a semiconductor package in accordance with example embodiments;
FIG. 2 is a plan view of a semiconductor package in accordance with example embodiments;
FIG. 1 is a cross-sectional view of a semiconductor package in accordance with example embodiments. FIG. 2 is a plan view of a semiconductor package in accordance with example embodiments. FIG. 3 is a cross-sectional view of a semiconductor package in accordance with some example embodiments.
The semiconductor packages shown in FIGS. 1 and 3 may be substantially the same, except for a lower insulation layer. FIGS. 1 and 3 are cross-sectional views taken along line I-I′ of FIG. 2. In FIG. 2, only the main elements are briefly shown, and some elements are omitted. Hereinafter, a semiconductor package in accordance with example embodiments will be described with reference to FIGS. 1 to 3.
Referring to FIGS. 1 to 3, the semiconductor package may include a package substrate 10, an interposer substrate 50, a semiconductor chip 200, a conductive bump 140, a redistribution layer 102, a lower passivation layer 110, an upper passivation layer 112, and a lower insulation layer 150.