Architecture for computing system package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Chieh-Yen Chen, Chuei-Tang Wang, Chung-Hao Tsai
Life of this patent
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Abstract
A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
Claims20
A method comprising:
- forming a reconstructed wafer comprising:
- forming a redistribution structure over a carrier;
- bonding a first plurality of memory dies over the redistribution structure;
- bonding a plurality of bridge dies over the redistribution structure;
- bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies;
- and
- bonding a second plurality of memory dies over the plurality of logic dies, wherein the plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
A package comprising:
- a redistribution structure;
- a first plurality of memory dies over the redistribution structure;
- a plurality of bridge dies over the redistribution structure;
- a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies, wherein each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, at least two of the plurality of logic dies;
- and
- a second plurality of memory dies over and bonded to the plurality of logic dies, wherein the plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
A package comprising:
- a reconstructed wafer comprising:
- a redistribution structure comprising a plurality of redistribution lines;
- a plurality of bridge dies over and bonded to the redistribution structure;
- a plurality of logic dies over and bonded to the plurality of bridge dies, wherein at least one of the plurality of bridge dies is bonded to corner regions of four of the plurality of logic dies;
- and
- a plurality of memory dies, wherein the plurality of memory dies are bonded to the plurality of logic dies.
Dependencies are inferred from the claim text.