Semiconductor device

A semiconductor device, comprising:

• a substrate including a first active region and a second active region, which are spaced apart from each other in a first horizontal direction with respect to an upper surface of the substrate;
• a first gate electrode crossing the first active region and extends in the first horizontal direction;
• a second gate electrode crossing the second active region and extends in the first horizontal direction;
• a gate separation pattern interposed between the first gate electrode and the second gate electrode;
• a first gate contact in contact with a top surface of the first gate electrode;
• and
• a first dummy gate contact in contact with a top surface of the second gate electrode,
• wherein a first voltage is applied to the first gate contact and no voltage is applied to the first dummy gate contact.

A semiconductor device, comprising:

• a substrate including a first active region and a second active region, which are spaced apart from each other in a first horizontal direction with respect to an upper surface of the substrate;
• a device isolation layer disposed in the substrate and defining the first and second active regions;
• a first active fin and a second active fin which protrude from the substrate in a vertical direction and disposed on the first and second active regions, respectively;
• a gate electrode crossing the first and second active fins in the first horizontal direction;
• a plurality of first channel patterns stacked in the vertical direction on each other on the first active fin;
• a plurality of second channel patterns stacked in the vertical direction on each other on the second active fin;
• a gate contact in contact with a top surface of the gate electrode;
• and
• a dummy gate contact spaced apart from the gate contact and in contact with the top surface of the gate electrode,
• wherein the gate electrode is configured to surround each of the plurality of first and second channel patterns, and
• wherein the gate contact overlaps the device isolation layer and the dummy gate contact overlaps the first active fin.