Three dimensional integrated circuit with monolithic inter-tier vias (MIV)
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin, Wei-An Lai
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Abstract
A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.
Claims20
A method, comprising:
- selecting a first plurality of lower tier cells each having a first cell height;
- selecting a second plurality of upper tier cells having the first cell height;
- reducing the first cell height by a predetermined scaling factor such that the first cell height is scaled to a second cell height;
- placing the scaled first plurality of lower tier cells on a lower tier;
- placing the scaled second plurality of upper tier cells on an upper tier over the lower tier;
- laterally separating at least two of the upper tier cells by a predetermined lateral space;
- enlarging the second cell height to the first cell height after the placing of the scaled first plurality of lower tier cells on the lower tier and the placing of the scaled second plurality of upper tier cells on the upper tier;
- and
- determining conductive routings for the first plurality of lower tier cells and the second plurality of upper tier cells.
A system, comprising:
- a processor;
- computer readable media accessible by the processor, the computer readable media storing a cell library defining a plurality of cells and instructions that when executed by the processor implement a method, comprising:
- receiving an integrated circuit design;
- selecting a first plurality of cells based on the integrated circuit design;
- selecting a second plurality of cells based on the integrated circuit design;
- determining a two-dimensional (2D) layout of the first plurality of cells for a lower tier of a monolithic three-dimensional (3D) integrated circuit (IC);
- determining a 2D layout of the second plurality of cells and a plurality of predetermined open spaces for an upper tier of the monolithic 3D IC;
- determining first conductive routings for the 2D layout of the first plurality of cells;
- determining second conductive routings for the 2D layout of the second plurality of cells;
- and
- determining a conductive connection of the first conductive routings and the second conductive routings with a monolithic inter-tier via (MIV) that extends through at least one of the predetermined open spaces.
A system, comprising:
- a processor;
- computer readable media accessible by the processor, the computer readable media storing a cell library defining a plurality of cells and instructions that when executed by the processor implement a method, comprising:
- providing a lower tier cell having a first cell height;
- providing first and second upper tier cells each having the first cell height;
- reducing the first cell height by a predetermined scaling factor such that the first cell height is scaled to a second cell height;
- placing the scaled lower tier cell on a lower tier;
- placing the first and second upper tier cells on an upper tier over the lower tier such that the first and second upper tier cells are laterally separated by a predetermined lateral space;
- and
- electrically connecting the lower tier cell and the first upper tier cell by a monolithic inter-tier via (MIV) extending from the lower tier through the predetermined lateral space to the upper tier.
Dependencies are inferred from the claim text.